Commit 0781b860 authored by Juergen Ributzka's avatar Juergen Ributzka
Browse files

[FastISel][AArch64] Use the proper FMOV instruction to materialize a +0.0. 

Use FMOVWSr/FMOVXDr instead of FMOVSr/FMOVDr, which have the proper register
class to be used with the zero register. This makes the MachineInstruction
verifier happy again.

This is related to <rdar://problem/18027157>.

llvm-svn: 216040
parent a0b988cb

llvm/lib/Target/AArch64/AArch64FastISel.cpp

+1 −1
Original line number Diff line number Diff line
@@ -291,7 +291,7 @@ unsigned AArch64FastISel::AArch64MaterializeFP(const ConstantFP *CFP, MVT VT) { 
    // register, because the immediate version of fmov cannot encode zero.

    if (Val.isPosZero()) {

      unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR;

      unsigned Opc = Is64Bit ? AArch64::FMOVDr : AArch64::FMOVSr;

      unsigned Opc = Is64Bit ? AArch64::FMOVXDr : AArch64::FMOVWSr;

      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)

        .addReg(ZReg, getKillRegState(true));

      return ResultReg;

llvm/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll

+1 −1
Original line number Diff line number Diff line 
; RUN: llc -O0 -fast-isel-abort -mtriple=arm64-apple-darwin < %s | FileCheck %s

; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s



; Materialize using fmov

define float @fmov_float1() {