Loading llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +2 −2 Original line number Diff line number Diff line Loading @@ -10895,8 +10895,8 @@ static SDValue getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op, const TargetLowering &TLI = DAG.getTargetLoweringInfo(); SDLoc DL(Op); EVT OpVT = Op.getValueType(); assert(OpVT.isScalableVector() && TLI.isTypeLegal(OpVT) && assert(Op.getValueType().isScalableVector() && TLI.isTypeLegal(Op.getValueType()) && "Expected legal scalable vector type!"); // Ensure target specific opcodes are using legal type. Loading Loading
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +2 −2 Original line number Diff line number Diff line Loading @@ -10895,8 +10895,8 @@ static SDValue getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op, const TargetLowering &TLI = DAG.getTargetLoweringInfo(); SDLoc DL(Op); EVT OpVT = Op.getValueType(); assert(OpVT.isScalableVector() && TLI.isTypeLegal(OpVT) && assert(Op.getValueType().isScalableVector() && TLI.isTypeLegal(Op.getValueType()) && "Expected legal scalable vector type!"); // Ensure target specific opcodes are using legal type. Loading