Commit 020041d9 authored by Krzysztof Parzyszek's avatar Krzysztof Parzyszek
Browse files

Update spelling of {analyze,insert,remove}Branch in strings and comments 

These names have been changed from CamelCase to camelCase, but there were
many places (comments mostly) that still used the old names.

This change is NFC.
parent 1fbb1d6d

libcxxabi/test/test_demangle.pass.cpp

+9 −9
Original line number Diff line number Diff line
@@ -12990,9 +12990,9 @@ const char* cases[][2] = 
    {"_ZN4llvm3X8621GetCondBranchFromCondENS0_8CondCodeE", "llvm::X86::GetCondBranchFromCond(llvm::X86::CondCode)"},

    {"_ZN4llvm3X8626GetOppositeBranchConditionENS0_8CondCodeE", "llvm::X86::GetOppositeBranchCondition(llvm::X86::CondCode)"},

    {"_ZNK4llvm12X86InstrInfo24isUnpredicatedTerminatorEPKNS_12MachineInstrE", "llvm::X86InstrInfo::isUnpredicatedTerminator(llvm::MachineInstr const*) const"},

    {"_ZNK4llvm12X86InstrInfo13AnalyzeBranchERNS_17MachineBasicBlockERPS1_S4_RNS_15SmallVectorImplINS_14MachineOperandEEEb", "llvm::X86InstrInfo::AnalyzeBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*&, llvm::MachineBasicBlock*&, llvm::SmallVectorImpl<llvm::MachineOperand>&, bool) const"},

    {"_ZNK4llvm12X86InstrInfo12RemoveBranchERNS_17MachineBasicBlockE", "llvm::X86InstrInfo::RemoveBranch(llvm::MachineBasicBlock&) const"},

    {"_ZNK4llvm12X86InstrInfo12InsertBranchERNS_17MachineBasicBlockEPS1_S3_RKNS_15SmallVectorImplINS_14MachineOperandEEENS_8DebugLocE", "llvm::X86InstrInfo::InsertBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::SmallVectorImpl<llvm::MachineOperand> const&, llvm::DebugLoc) const"},

    {"_ZNK4llvm12X86InstrInfo13analyzeBranchERNS_17MachineBasicBlockERPS1_S4_RNS_15SmallVectorImplINS_14MachineOperandEEEb", "llvm::X86InstrInfo::analyzeBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*&, llvm::MachineBasicBlock*&, llvm::SmallVectorImpl<llvm::MachineOperand>&, bool) const"},

    {"_ZNK4llvm12X86InstrInfo12removeBranchERNS_17MachineBasicBlockE", "llvm::X86InstrInfo::removeBranch(llvm::MachineBasicBlock&) const"},

    {"_ZNK4llvm12X86InstrInfo12insertBranchERNS_17MachineBasicBlockEPS1_S3_RKNS_15SmallVectorImplINS_14MachineOperandEEENS_8DebugLocE", "llvm::X86InstrInfo::insertBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::SmallVectorImpl<llvm::MachineOperand> const&, llvm::DebugLoc) const"},

    {"_ZNK4llvm12X86InstrInfo11copyPhysRegERNS_17MachineBasicBlockENS_14ilist_iteratorINS_12MachineInstrEEENS_8DebugLocEjjb", "llvm::X86InstrInfo::copyPhysReg(llvm::MachineBasicBlock&, llvm::ilist_iterator<llvm::MachineInstr>, llvm::DebugLoc, unsigned int, unsigned int, bool) const"},

    {"_ZNK4llvm12X86InstrInfo19storeRegToStackSlotERNS_17MachineBasicBlockENS_14ilist_iteratorINS_12MachineInstrEEEjbiPKNS_19TargetRegisterClassEPKNS_18TargetRegisterInfoE", "llvm::X86InstrInfo::storeRegToStackSlot(llvm::MachineBasicBlock&, llvm::ilist_iterator<llvm::MachineInstr>, unsigned int, bool, int, llvm::TargetRegisterClass const*, llvm::TargetRegisterInfo const*) const"},

    {"_ZN4llvm17addFrameReferenceERKNS_19MachineInstrBuilderEii", "llvm::addFrameReference(llvm::MachineInstrBuilder const&, int, int)"},
@@ -13545,9 +13545,9 @@ const char* cases[][2] = 
    {"_ZNK4llvm16ARMBaseInstrInfo28CreateTargetHazardRecognizerEPKNS_13TargetMachineEPKNS_11ScheduleDAGE", "llvm::ARMBaseInstrInfo::CreateTargetHazardRecognizer(llvm::TargetMachine const*, llvm::ScheduleDAG const*) const"},

    {"_ZNK4llvm16ARMBaseInstrInfo34CreateTargetPostRAHazardRecognizerEPKNS_18InstrItineraryDataEPKNS_11ScheduleDAGE", "llvm::ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer(llvm::InstrItineraryData const*, llvm::ScheduleDAG const*) const"},

    {"_ZNK4llvm16ARMBaseInstrInfo21convertToThreeAddressERNS_14ilist_iteratorINS_17MachineBasicBlockEEERNS1_INS_12MachineInstrEEEPNS_13LiveVariablesE", "llvm::ARMBaseInstrInfo::convertToThreeAddress(llvm::ilist_iterator<llvm::MachineBasicBlock>&, llvm::ilist_iterator<llvm::MachineInstr>&, llvm::LiveVariables*) const"},

    {"_ZNK4llvm16ARMBaseInstrInfo13AnalyzeBranchERNS_17MachineBasicBlockERPS1_S4_RNS_15SmallVectorImplINS_14MachineOperandEEEb", "llvm::ARMBaseInstrInfo::AnalyzeBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*&, llvm::MachineBasicBlock*&, llvm::SmallVectorImpl<llvm::MachineOperand>&, bool) const"},

    {"_ZNK4llvm16ARMBaseInstrInfo12RemoveBranchERNS_17MachineBasicBlockE", "llvm::ARMBaseInstrInfo::RemoveBranch(llvm::MachineBasicBlock&) const"},

    {"_ZNK4llvm16ARMBaseInstrInfo12InsertBranchERNS_17MachineBasicBlockEPS1_S3_RKNS_15SmallVectorImplINS_14MachineOperandEEENS_8DebugLocE", "llvm::ARMBaseInstrInfo::InsertBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::SmallVectorImpl<llvm::MachineOperand> const&, llvm::DebugLoc) const"},

    {"_ZNK4llvm16ARMBaseInstrInfo13analyzeBranchERNS_17MachineBasicBlockERPS1_S4_RNS_15SmallVectorImplINS_14MachineOperandEEEb", "llvm::ARMBaseInstrInfo::analyzeBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*&, llvm::MachineBasicBlock*&, llvm::SmallVectorImpl<llvm::MachineOperand>&, bool) const"},

    {"_ZNK4llvm16ARMBaseInstrInfo12removeBranchERNS_17MachineBasicBlockE", "llvm::ARMBaseInstrInfo::removeBranch(llvm::MachineBasicBlock&) const"},

    {"_ZNK4llvm16ARMBaseInstrInfo12insertBranchERNS_17MachineBasicBlockEPS1_S3_RKNS_15SmallVectorImplINS_14MachineOperandEEENS_8DebugLocE", "llvm::ARMBaseInstrInfo::insertBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::SmallVectorImpl<llvm::MachineOperand> const&, llvm::DebugLoc) const"},

    {"_ZNK4llvm16ARMBaseInstrInfo22ReverseBranchConditionERNS_15SmallVectorImplINS_14MachineOperandEEE", "llvm::ARMBaseInstrInfo::ReverseBranchCondition(llvm::SmallVectorImpl<llvm::MachineOperand>&) const"},

    {"_ZNK4llvm16ARMBaseInstrInfo20PredicateInstructionEPNS_12MachineInstrERKNS_15SmallVectorImplINS_14MachineOperandEEE", "llvm::ARMBaseInstrInfo::PredicateInstruction(llvm::MachineInstr*, llvm::SmallVectorImpl<llvm::MachineOperand> const&) const"},

    {"_ZN4llvm27getMatchingCondBranchOpcodeEi", "llvm::getMatchingCondBranchOpcode(int)"},
@@ -14257,9 +14257,9 @@ const char* cases[][2] = 
    {"_ZNK4llvm15TargetInstrInfo19isLoadFromStackSlotEPKNS_12MachineInstrERi", "llvm::TargetInstrInfo::isLoadFromStackSlot(llvm::MachineInstr const*, int&) const"},

    {"_ZNK4llvm15TargetInstrInfo18isStoreToStackSlotEPKNS_12MachineInstrERi", "llvm::TargetInstrInfo::isStoreToStackSlot(llvm::MachineInstr const*, int&) const"},

    {"_ZNK4llvm15TargetInstrInfo21convertToThreeAddressERNS_14ilist_iteratorINS_17MachineBasicBlockEEERNS1_INS_12MachineInstrEEEPNS_13LiveVariablesE", "llvm::TargetInstrInfo::convertToThreeAddress(llvm::ilist_iterator<llvm::MachineBasicBlock>&, llvm::ilist_iterator<llvm::MachineInstr>&, llvm::LiveVariables*) const"},

    {"_ZNK4llvm15TargetInstrInfo13AnalyzeBranchERNS_17MachineBasicBlockERPS1_S4_RNS_15SmallVectorImplINS_14MachineOperandEEEb", "llvm::TargetInstrInfo::AnalyzeBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*&, llvm::MachineBasicBlock*&, llvm::SmallVectorImpl<llvm::MachineOperand>&, bool) const"},

    {"_ZNK4llvm15TargetInstrInfo12RemoveBranchERNS_17MachineBasicBlockE", "llvm::TargetInstrInfo::RemoveBranch(llvm::MachineBasicBlock&) const"},

    {"_ZNK4llvm15TargetInstrInfo12InsertBranchERNS_17MachineBasicBlockEPS1_S3_RKNS_15SmallVectorImplINS_14MachineOperandEEENS_8DebugLocE", "llvm::TargetInstrInfo::InsertBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::SmallVectorImpl<llvm::MachineOperand> const&, llvm::DebugLoc) const"},

    {"_ZNK4llvm15TargetInstrInfo13analyzeBranchERNS_17MachineBasicBlockERPS1_S4_RNS_15SmallVectorImplINS_14MachineOperandEEEb", "llvm::TargetInstrInfo::analyzeBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*&, llvm::MachineBasicBlock*&, llvm::SmallVectorImpl<llvm::MachineOperand>&, bool) const"},

    {"_ZNK4llvm15TargetInstrInfo12removeBranchERNS_17MachineBasicBlockE", "llvm::TargetInstrInfo::removeBranch(llvm::MachineBasicBlock&) const"},

    {"_ZNK4llvm15TargetInstrInfo12insertBranchERNS_17MachineBasicBlockEPS1_S3_RKNS_15SmallVectorImplINS_14MachineOperandEEENS_8DebugLocE", "llvm::TargetInstrInfo::insertBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::SmallVectorImpl<llvm::MachineOperand> const&, llvm::DebugLoc) const"},

    {"_ZNK4llvm15TargetInstrInfo19isProfitableToIfCvtERNS_17MachineBasicBlockEjjff", "llvm::TargetInstrInfo::isProfitableToIfCvt(llvm::MachineBasicBlock&, unsigned int, unsigned int, float, float) const"},

    {"_ZNK4llvm15TargetInstrInfo19isProfitableToIfCvtERNS_17MachineBasicBlockEjjS2_jjff", "llvm::TargetInstrInfo::isProfitableToIfCvt(llvm::MachineBasicBlock&, unsigned int, unsigned int, llvm::MachineBasicBlock&, unsigned int, unsigned int, float, float) const"},

    {"_ZNK4llvm15TargetInstrInfo25isProfitableToDupForIfCvtERNS_17MachineBasicBlockEjff", "llvm::TargetInstrInfo::isProfitableToDupForIfCvt(llvm::MachineBasicBlock&, unsigned int, float, float) const"},

llvm/docs/WritingAnLLVMBackend.rst

+17 −17
Original line number Diff line number Diff line
@@ -1100,21 +1100,21 @@ Branch Folding and If Conversion 
--------------------------------



Performance can be improved by combining instructions or by eliminating

instructions that are never reached.  The ``AnalyzeBranch`` method in

instructions that are never reached.  The ``analyzeBranch`` method in

``XXXInstrInfo`` may be implemented to examine conditional instructions and

remove unnecessary instructions.  ``AnalyzeBranch`` looks at the end of a

remove unnecessary instructions.  ``analyzeBranch`` looks at the end of a

machine basic block (MBB) for opportunities for improvement, such as branch

folding and if conversion.  The ``BranchFolder`` and ``IfConverter`` machine

function passes (see the source files ``BranchFolding.cpp`` and

``IfConversion.cpp`` in the ``lib/CodeGen`` directory) call ``AnalyzeBranch``

``IfConversion.cpp`` in the ``lib/CodeGen`` directory) call ``analyzeBranch``

to improve the control flow graph that represents the instructions.



Several implementations of ``AnalyzeBranch`` (for ARM, Alpha, and X86) can be

examined as models for your own ``AnalyzeBranch`` implementation.  Since SPARC

does not implement a useful ``AnalyzeBranch``, the ARM target implementation is

Several implementations of ``analyzeBranch`` (for ARM, Alpha, and X86) can be

examined as models for your own ``analyzeBranch`` implementation.  Since SPARC

does not implement a useful ``analyzeBranch``, the ARM target implementation is

shown below.



``AnalyzeBranch`` returns a Boolean value and takes four parameters:

``analyzeBranch`` returns a Boolean value and takes four parameters:



* ``MachineBasicBlock &MBB`` --- The incoming block to be examined.
@@ -1130,12 +1130,12 @@ shown below. 
In the simplest case, if a block ends without a branch, then it falls through

to the successor block.  No destination blocks are specified for either ``TBB``

or ``FBB``, so both parameters return ``NULL``.  The start of the

``AnalyzeBranch`` (see code below for the ARM target) shows the function

``analyzeBranch`` (see code below for the ARM target) shows the function

parameters and the code for the simplest case.



.. code-block:: c++



  bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,

  bool ARMInstrInfo::analyzeBranch(MachineBasicBlock &MBB,

                                   MachineBasicBlock *&TBB,

                                   MachineBasicBlock *&FBB,

                                   std::vector<MachineOperand> &Cond) const
@@ -1145,7 +1145,7 @@ parameters and the code for the simplest case. 
      return false;



If a block ends with a single unconditional branch instruction, then

``AnalyzeBranch`` (shown below) should return the destination of that branch in

``analyzeBranch`` (shown below) should return the destination of that branch in

the ``TBB`` parameter.



.. code-block:: c++
@@ -1171,7 +1171,7 @@ instruction and return the penultimate branch in the ``TBB`` parameter. 


A block may end with a single conditional branch instruction that falls through

to successor block if the condition evaluates to false.  In that case,

``AnalyzeBranch`` (shown below) should return the destination of that

``analyzeBranch`` (shown below) should return the destination of that

conditional branch in the ``TBB`` parameter and a list of operands in the

``Cond`` parameter to evaluate the condition.
@@ -1186,7 +1186,7 @@ conditional branch in the ``TBB`` parameter and a list of operands in the 
    }



If a block ends with both a conditional branch and an ensuing unconditional

branch, then ``AnalyzeBranch`` (shown below) should return the conditional

branch, then ``analyzeBranch`` (shown below) should return the conditional

branch destination (assuming it corresponds to a conditional evaluation of

"``true``") in the ``TBB`` parameter and the unconditional branch destination

in the ``FBB`` (corresponding to a conditional evaluation of "``false``").  A
@@ -1209,14 +1209,14 @@ parameter. 
For the last two cases (ending with a single conditional branch or ending with

one conditional and one unconditional branch), the operands returned in the

``Cond`` parameter can be passed to methods of other instructions to create new

branches or perform other operations.  An implementation of ``AnalyzeBranch``

requires the helper methods ``RemoveBranch`` and ``InsertBranch`` to manage

branches or perform other operations.  An implementation of ``analyzeBranch``

requires the helper methods ``removeBranch`` and ``insertBranch`` to manage

subsequent operations.



``AnalyzeBranch`` should return false indicating success in most circumstances.

``AnalyzeBranch`` should only return true when the method is stumped about what

``analyzeBranch`` should return false indicating success in most circumstances.

``analyzeBranch`` should only return true when the method is stumped about what

to do, for example, if a block has three terminating branches.

``AnalyzeBranch`` may return true if it encounters a terminator it cannot

``analyzeBranch`` may return true if it encounters a terminator it cannot

handle, such as an indirect branch.



.. _instruction-selector:

llvm/include/llvm/CodeGen/MachineInstr.h

+3 −3
Original line number Diff line number Diff line
@@ -701,7 +701,7 @@ public: 


  /// Returns true if this is a conditional, unconditional, or indirect branch.

  /// Predicates below can be used to discriminate between

  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to

  /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to

  /// get more information.

  bool isBranch(QueryType Type = AnyInBundle) const {

    return hasProperty(MCID::Branch, Type);
@@ -715,7 +715,7 @@ public: 


  /// Return true if this is a branch which may fall

  /// through to the next instruction or may transfer control flow to some other

  /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more

  /// block.  The TargetInstrInfo::analyzeBranch method can be used to get more

  /// information about this branch.

  bool isConditionalBranch(QueryType Type = AnyInBundle) const {

    return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
@@ -723,7 +723,7 @@ public: 


  /// Return true if this is a branch which always

  /// transfers control flow to some other block.  The

  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information

  /// TargetInstrInfo::analyzeBranch method can be used to get more information

  /// about this branch.

  bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {

    return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type);

llvm/include/llvm/CodeGen/TargetInstrInfo.h

+7 −7
Original line number Diff line number Diff line
@@ -644,7 +644,7 @@ public: 
  }



  /// Remove the branching code at the end of the specific MBB.

  /// This is only invoked in cases where AnalyzeBranch returns success. It

  /// This is only invoked in cases where analyzeBranch returns success. It

  /// returns the number of instructions that were removed.

  /// If \p BytesRemoved is non-null, report the change in code size from the

  /// removed instructions.
@@ -654,13 +654,13 @@ public: 
  }



  /// Insert branch code into the end of the specified MachineBasicBlock. The

  /// operands to this method are the same as those returned by AnalyzeBranch.

  /// This is only invoked in cases where AnalyzeBranch returns success. It

  /// operands to this method are the same as those returned by analyzeBranch.

  /// This is only invoked in cases where analyzeBranch returns success. It

  /// returns the number of instructions inserted. If \p BytesAdded is non-null,

  /// report the change in code size from the added instructions.

  ///

  /// It is also invoked by tail merging to add unconditional branches in

  /// cases where AnalyzeBranch doesn't apply because there was no original

  /// cases where analyzeBranch doesn't apply because there was no original

  /// branch to analyze.  At least this much must be implemented, else tail

  /// merging needs to be disabled.

  ///
@@ -837,7 +837,7 @@ public: 
  /// Some x86 implementations have 2-cycle cmov instructions.

  ///

  /// @param MBB         Block where select instruction would be inserted.

  /// @param Cond        Condition returned by AnalyzeBranch.

  /// @param Cond        Condition returned by analyzeBranch.

  /// @param TrueReg     Virtual register to select when Cond is true.

  /// @param FalseReg    Virtual register to select when Cond is false.

  /// @param CondCycles  Latency from Cond+Branch to select output.
@@ -854,7 +854,7 @@ public: 
  /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.

  ///

  /// This function can only be called after canInsertSelect() returned true.

  /// The condition in Cond comes from AnalyzeBranch, and it can be assumed

  /// The condition in Cond comes from analyzeBranch, and it can be assumed

  /// that the same flags or registers required by Cond are available at the

  /// insertion point.

  ///
@@ -862,7 +862,7 @@ public: 
  /// @param I        Insertion point.

  /// @param DL       Source location for debugging.

  /// @param DstReg   Virtual register to be defined by select instruction.

  /// @param Cond     Condition as computed by AnalyzeBranch.

  /// @param Cond     Condition as computed by analyzeBranch.

  /// @param TrueReg  Virtual register to copy when Cond is true.

  /// @param FalseReg Virtual register to copy when Cons is false.

  virtual void insertSelect(MachineBasicBlock &MBB,

llvm/include/llvm/MC/MCInstrDesc.h

+3 −3
Original line number Diff line number Diff line
@@ -300,7 +300,7 @@ public: 


  /// Returns true if this is a conditional, unconditional, or

  /// indirect branch.  Predicates below can be used to discriminate between

  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to

  /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to

  /// get more information.

  bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
@@ -310,7 +310,7 @@ public: 


  /// Return true if this is a branch which may fall

  /// through to the next instruction or may transfer control flow to some other

  /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more

  /// block.  The TargetInstrInfo::analyzeBranch method can be used to get more

  /// information about this branch.

  bool isConditionalBranch() const {

    return isBranch() && !isBarrier() && !isIndirectBranch();
@@ -318,7 +318,7 @@ public: 


  /// Return true if this is a branch which always

  /// transfers control flow to some other block.  The

  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information

  /// TargetInstrInfo::analyzeBranch method can be used to get more information

  /// about this branch.

  bool isUnconditionalBranch() const {

    return isBranch() && isBarrier() && !isIndirectBranch();