Commit 01a4b831 authored by Michael Liao's avatar Michael Liao
Browse files

[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. 

Summary:
- `dead-mi-elimination` assumes MIR in the SSA form and cannot be
  arranged after phi elimination or DeSSA. It's enhanced to handle the
  dead register definition by skipping use check on it. Once a register
  def is `dead`, all its uses, if any, should be `undef`.
- Re-arrange the DIE in RA phase for AMDGPU by placing it directly after
  `detect-dead-lanes`.
- Many relevant tests are refined due to different register assignment.

Reviewers: rampitec, qcolombet, sunfish

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72709
parent 47c6ab2b

llvm/lib/CodeGen/DeadMachineInstructionElim.cpp

+9 −0
Original line number Diff line number Diff line
@@ -82,6 +82,15 @@ bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const { 
        if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))

          return false;

      } else {

        if (MO.isDead()) {

#ifndef NDEBUG

          // Sanity check on uses of this dead register. All of them should be

          // 'undef'.

          for (auto &U : MRI->use_nodbg_operands(Reg))

            assert(U.isUndef() && "'Undef' use on a 'dead' register is found!");

#endif

          continue;

        }

        for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {

          if (&Use != MI)

            // This def has a non-debug use. Don't delete the instruction!

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

+1 −1
Original line number Diff line number Diff line
@@ -948,7 +948,7 @@ void GCNPassConfig::addOptimizedRegAlloc() { 
  insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);



  if (EnableDCEInRA)

    insertPass(&RenameIndependentSubregsID, &DeadMachineInstructionElimID);

    insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);



  TargetPassConfig::addOptimizedRegAlloc();

}

llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll

+16 −16
Original line number Diff line number Diff line
@@ -1205,20 +1205,20 @@ define amdgpu_kernel void @add_i64_constant(i64 addrspace(1)* %out) { 
;

; GFX1064-LABEL: add_i64_constant:

; GFX1064:       ; %bb.0: ; %entry

; GFX1064-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0

; GFX1064-NEXT:    v_cmp_ne_u32_e64 s[4:5], 1, 0

; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24

; GFX1064-NEXT:    ; implicit-def: $vgpr1_vgpr2

; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s2, 0

; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s3, v0

; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s4, 0

; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s5, v0

; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0

; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc

; GFX1064-NEXT:    s_and_saveexec_b64 s[2:3], vcc

; GFX1064-NEXT:    ; mask branch BB5_2

; GFX1064-NEXT:    s_cbranch_execz BB5_2

; GFX1064-NEXT:  BB5_1:

; GFX1064-NEXT:    s_bcnt1_i32_b64 s2, s[2:3]

; GFX1064-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]

; GFX1064-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo

; GFX1064-NEXT:    v_mul_hi_u32_u24_e64 v2, s2, 5

; GFX1064-NEXT:    v_mul_u32_u24_e64 v1, s2, 5

; GFX1064-NEXT:    v_mul_hi_u32_u24_e64 v2, s4, 5

; GFX1064-NEXT:    v_mul_u32_u24_e64 v1, s4, 5

; GFX1064-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)

; GFX1064-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX1064-NEXT:    ds_add_rtn_u64 v[1:2], v3, v[1:2]
@@ -1227,7 +1227,7 @@ define amdgpu_kernel void @add_i64_constant(i64 addrspace(1)* %out) { 
; GFX1064-NEXT:    buffer_gl1_inv

; GFX1064-NEXT:  BB5_2:

; GFX1064-NEXT:    v_nop

; GFX1064-NEXT:    s_or_b64 exec, exec, s[4:5]

; GFX1064-NEXT:    s_or_b64 exec, exec, s[2:3]

; GFX1064-NEXT:    v_readfirstlane_b32 s2, v1

; GFX1064-NEXT:    v_readfirstlane_b32 s3, v2

; GFX1064-NEXT:    v_mad_u64_u32 v[0:1], s[2:3], v0, 5, s[2:3]
@@ -2310,20 +2310,20 @@ define amdgpu_kernel void @sub_i64_constant(i64 addrspace(1)* %out) { 
;

; GFX1064-LABEL: sub_i64_constant:

; GFX1064:       ; %bb.0: ; %entry

; GFX1064-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, 0

; GFX1064-NEXT:    v_cmp_ne_u32_e64 s[4:5], 1, 0

; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24

; GFX1064-NEXT:    ; implicit-def: $vgpr1_vgpr2

; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s2, 0

; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s3, v0

; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s4, 0

; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s5, v0

; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0

; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc

; GFX1064-NEXT:    s_and_saveexec_b64 s[2:3], vcc

; GFX1064-NEXT:    ; mask branch BB11_2

; GFX1064-NEXT:    s_cbranch_execz BB11_2

; GFX1064-NEXT:  BB11_1:

; GFX1064-NEXT:    s_bcnt1_i32_b64 s2, s[2:3]

; GFX1064-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]

; GFX1064-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo

; GFX1064-NEXT:    v_mul_hi_u32_u24_e64 v2, s2, 5

; GFX1064-NEXT:    v_mul_u32_u24_e64 v1, s2, 5

; GFX1064-NEXT:    v_mul_hi_u32_u24_e64 v2, s4, 5

; GFX1064-NEXT:    v_mul_u32_u24_e64 v1, s4, 5

; GFX1064-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)

; GFX1064-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX1064-NEXT:    ds_sub_rtn_u64 v[1:2], v3, v[1:2]
@@ -2332,7 +2332,7 @@ define amdgpu_kernel void @sub_i64_constant(i64 addrspace(1)* %out) { 
; GFX1064-NEXT:    buffer_gl1_inv

; GFX1064-NEXT:  BB11_2:

; GFX1064-NEXT:    v_nop

; GFX1064-NEXT:    s_or_b64 exec, exec, s[4:5]

; GFX1064-NEXT:    s_or_b64 exec, exec, s[2:3]

; GFX1064-NEXT:    v_readfirstlane_b32 s2, v1

; GFX1064-NEXT:    v_mul_u32_u24_e32 v1, 5, v0

; GFX1064-NEXT:    v_readfirstlane_b32 s3, v2

llvm/test/CodeGen/AMDGPU/bswap.ll

+98 −98
Original line number Diff line number Diff line
@@ -189,41 +189,41 @@ define amdgpu_kernel void @test_bswap_v8i32(<8 x i32> addrspace(1)* %out, <8 x i 
;

; VI-LABEL: test_bswap_v8i32:

; VI:       ; %bb.0:

; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24

; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24

; VI-NEXT:    s_mov_b32 s12, 0xff00ff

; VI-NEXT:    s_mov_b32 s11, 0xf000

; VI-NEXT:    s_mov_b32 s10, -1

; VI-NEXT:    s_mov_b32 s3, 0xf000

; VI-NEXT:    s_mov_b32 s2, -1

; VI-NEXT:    s_waitcnt lgkmcnt(0)

; VI-NEXT:    s_mov_b32 s8, s0

; VI-NEXT:    s_mov_b32 s9, s1

; VI-NEXT:    s_load_dwordx8 s[0:7], s[2:3], 0x0

; VI-NEXT:    s_mov_b32 s0, s4

; VI-NEXT:    s_mov_b32 s1, s5

; VI-NEXT:    s_load_dwordx8 s[4:11], s[6:7], 0x0

; VI-NEXT:    s_waitcnt lgkmcnt(0)

; VI-NEXT:    v_alignbit_b32 v0, s3, s3, 8

; VI-NEXT:    v_alignbit_b32 v1, s3, s3, 24

; VI-NEXT:    v_alignbit_b32 v0, s7, s7, 8

; VI-NEXT:    v_alignbit_b32 v1, s7, s7, 24

; VI-NEXT:    v_bfi_b32 v3, s12, v1, v0

; VI-NEXT:    v_alignbit_b32 v2, s2, s2, 8

; VI-NEXT:    v_alignbit_b32 v4, s2, s2, 24

; VI-NEXT:    v_alignbit_b32 v0, s1, s1, 8

; VI-NEXT:    v_alignbit_b32 v1, s1, s1, 24

; VI-NEXT:    v_alignbit_b32 v2, s6, s6, 8

; VI-NEXT:    v_alignbit_b32 v4, s6, s6, 24

; VI-NEXT:    v_alignbit_b32 v0, s5, s5, 8

; VI-NEXT:    v_alignbit_b32 v1, s5, s5, 24

; VI-NEXT:    v_bfi_b32 v2, s12, v4, v2

; VI-NEXT:    v_bfi_b32 v1, s12, v1, v0

; VI-NEXT:    v_alignbit_b32 v0, s0, s0, 8

; VI-NEXT:    v_alignbit_b32 v4, s0, s0, 24

; VI-NEXT:    v_alignbit_b32 v0, s4, s4, 8

; VI-NEXT:    v_alignbit_b32 v4, s4, s4, 24

; VI-NEXT:    v_bfi_b32 v0, s12, v4, v0

; VI-NEXT:    v_alignbit_b32 v4, s7, s7, 8

; VI-NEXT:    v_alignbit_b32 v5, s7, s7, 24

; VI-NEXT:    v_alignbit_b32 v4, s11, s11, 8

; VI-NEXT:    v_alignbit_b32 v5, s11, s11, 24

; VI-NEXT:    v_bfi_b32 v7, s12, v5, v4

; VI-NEXT:    v_alignbit_b32 v4, s6, s6, 8

; VI-NEXT:    v_alignbit_b32 v5, s6, s6, 24

; VI-NEXT:    v_alignbit_b32 v4, s10, s10, 8

; VI-NEXT:    v_alignbit_b32 v5, s10, s10, 24

; VI-NEXT:    v_bfi_b32 v6, s12, v5, v4

; VI-NEXT:    v_alignbit_b32 v4, s5, s5, 8

; VI-NEXT:    v_alignbit_b32 v5, s5, s5, 24

; VI-NEXT:    v_alignbit_b32 v4, s9, s9, 8

; VI-NEXT:    v_alignbit_b32 v5, s9, s9, 24

; VI-NEXT:    v_bfi_b32 v5, s12, v5, v4

; VI-NEXT:    v_alignbit_b32 v4, s4, s4, 8

; VI-NEXT:    v_alignbit_b32 v8, s4, s4, 24

; VI-NEXT:    v_alignbit_b32 v4, s8, s8, 8

; VI-NEXT:    v_alignbit_b32 v8, s8, s8, 24

; VI-NEXT:    v_bfi_b32 v4, s12, v8, v4

; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16

; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0

; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16

; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0

; VI-NEXT:    s_endpgm

  %val = load <8 x i32>, <8 x i32> addrspace(1)* %in, align 32

  %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %val) nounwind readnone
@@ -234,11 +234,11 @@ define amdgpu_kernel void @test_bswap_v8i32(<8 x i32> addrspace(1)* %out, <8 x i 
define amdgpu_kernel void @test_bswap_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {

; SI-LABEL: test_bswap_i64:

; SI:       ; %bb.0:

; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9

; SI-NEXT:    s_mov_b32 s7, 0xf000

; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9

; SI-NEXT:    s_mov_b32 s3, 0xf000

; SI-NEXT:    s_waitcnt lgkmcnt(0)

; SI-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x0

; SI-NEXT:    s_mov_b32 s6, -1

; SI-NEXT:    s_load_dwordx2 s[6:7], s[6:7], 0x0

; SI-NEXT:    s_mov_b32 s2, -1

; SI-NEXT:    s_mov_b32 s19, 0xff0000

; SI-NEXT:    s_mov_b32 s9, 0

; SI-NEXT:    s_mov_b32 s15, 0xff00
@@ -247,34 +247,34 @@ define amdgpu_kernel void @test_bswap_i64(i64 addrspace(1)* %out, i64 addrspace( 
; SI-NEXT:    s_mov_b32 s14, s9

; SI-NEXT:    s_mov_b32 s16, s9

; SI-NEXT:    s_mov_b32 s18, s9

; SI-NEXT:    s_mov_b32 s4, s0

; SI-NEXT:    s_mov_b32 s5, s1

; SI-NEXT:    s_mov_b32 s0, s4

; SI-NEXT:    s_mov_b32 s1, s5

; SI-NEXT:    s_waitcnt lgkmcnt(0)

; SI-NEXT:    v_mov_b32_e32 v0, s2

; SI-NEXT:    v_alignbit_b32 v1, s3, v0, 24

; SI-NEXT:    v_alignbit_b32 v0, s3, v0, 8

; SI-NEXT:    s_lshr_b32 s8, s3, 24

; SI-NEXT:    s_lshr_b32 s10, s3, 8

; SI-NEXT:    s_lshl_b64 s[0:1], s[2:3], 8

; SI-NEXT:    s_lshl_b64 s[20:21], s[2:3], 24

; SI-NEXT:    s_lshl_b32 s17, s2, 24

; SI-NEXT:    s_lshl_b32 s0, s2, 8

; SI-NEXT:    v_mov_b32_e32 v0, s6

; SI-NEXT:    v_alignbit_b32 v1, s7, v0, 24

; SI-NEXT:    v_alignbit_b32 v0, s7, v0, 8

; SI-NEXT:    s_lshr_b32 s8, s7, 24

; SI-NEXT:    s_lshr_b32 s10, s7, 8

; SI-NEXT:    s_lshl_b64 s[4:5], s[6:7], 8

; SI-NEXT:    s_lshl_b64 s[20:21], s[6:7], 24

; SI-NEXT:    s_lshl_b32 s17, s6, 24

; SI-NEXT:    s_lshl_b32 s4, s6, 8

; SI-NEXT:    v_and_b32_e32 v1, s19, v1

; SI-NEXT:    v_and_b32_e32 v0, 0xff000000, v0

; SI-NEXT:    s_and_b32 s10, s10, s15

; SI-NEXT:    s_and_b32 s13, s1, 0xff

; SI-NEXT:    s_and_b32 s13, s5, 0xff

; SI-NEXT:    s_and_b32 s15, s21, s15

; SI-NEXT:    s_and_b32 s19, s0, s19

; SI-NEXT:    s_and_b32 s19, s4, s19

; SI-NEXT:    v_or_b32_e32 v0, v0, v1

; SI-NEXT:    s_or_b64 s[0:1], s[10:11], s[8:9]

; SI-NEXT:    s_or_b64 s[2:3], s[14:15], s[12:13]

; SI-NEXT:    s_or_b64 s[4:5], s[10:11], s[8:9]

; SI-NEXT:    s_or_b64 s[6:7], s[14:15], s[12:13]

; SI-NEXT:    s_or_b64 s[8:9], s[16:17], s[18:19]

; SI-NEXT:    v_or_b32_e32 v0, s0, v0

; SI-NEXT:    v_mov_b32_e32 v1, s1

; SI-NEXT:    s_or_b64 s[0:1], s[8:9], s[2:3]

; SI-NEXT:    v_or_b32_e32 v0, s0, v0

; SI-NEXT:    v_or_b32_e32 v1, s1, v1

; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0

; SI-NEXT:    v_or_b32_e32 v0, s4, v0

; SI-NEXT:    v_mov_b32_e32 v1, s5

; SI-NEXT:    s_or_b64 s[4:5], s[8:9], s[6:7]

; SI-NEXT:    v_or_b32_e32 v0, s4, v0

; SI-NEXT:    v_or_b32_e32 v1, s5, v1

; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0

; SI-NEXT:    s_endpgm

;

; VI-LABEL: test_bswap_i64:
@@ -328,47 +328,47 @@ define amdgpu_kernel void @test_bswap_i64(i64 addrspace(1)* %out, i64 addrspace( 
define amdgpu_kernel void @test_bswap_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) nounwind {

; SI-LABEL: test_bswap_v2i64:

; SI:       ; %bb.0:

; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9

; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9

; SI-NEXT:    s_mov_b32 s3, 0xf000

; SI-NEXT:    s_mov_b32 s2, -1

; SI-NEXT:    s_mov_b32 s31, 0xff0000

; SI-NEXT:    s_waitcnt lgkmcnt(0)

; SI-NEXT:    s_load_dwordx4 s[4:7], s[10:11], 0x0

; SI-NEXT:    s_mov_b32 s11, 0

; SI-NEXT:    s_load_dwordx4 s[8:11], s[6:7], 0x0

; SI-NEXT:    s_mov_b32 s7, 0

; SI-NEXT:    s_mov_b32 s22, 0xff000000

; SI-NEXT:    s_mov_b32 s27, 0xff00

; SI-NEXT:    s_movk_i32 s25, 0xff

; SI-NEXT:    s_mov_b32 s13, s11

; SI-NEXT:    s_mov_b32 s14, s11

; SI-NEXT:    s_mov_b32 s16, s11

; SI-NEXT:    s_mov_b32 s18, s11

; SI-NEXT:    s_mov_b32 s20, s11

; SI-NEXT:    s_mov_b32 s23, s11

; SI-NEXT:    s_mov_b32 s24, s11

; SI-NEXT:    s_mov_b32 s26, s11

; SI-NEXT:    s_mov_b32 s28, s11

; SI-NEXT:    s_mov_b32 s30, s11

; SI-NEXT:    s_mov_b32 s0, s8

; SI-NEXT:    s_mov_b32 s1, s9

; SI-NEXT:    s_mov_b32 s13, s7

; SI-NEXT:    s_mov_b32 s14, s7

; SI-NEXT:    s_mov_b32 s16, s7

; SI-NEXT:    s_mov_b32 s18, s7

; SI-NEXT:    s_mov_b32 s20, s7

; SI-NEXT:    s_mov_b32 s23, s7

; SI-NEXT:    s_mov_b32 s24, s7

; SI-NEXT:    s_mov_b32 s26, s7

; SI-NEXT:    s_mov_b32 s28, s7

; SI-NEXT:    s_mov_b32 s30, s7

; SI-NEXT:    s_mov_b32 s0, s4

; SI-NEXT:    s_mov_b32 s1, s5

; SI-NEXT:    s_waitcnt lgkmcnt(0)

; SI-NEXT:    v_mov_b32_e32 v0, s6

; SI-NEXT:    v_alignbit_b32 v1, s7, v0, 24

; SI-NEXT:    v_alignbit_b32 v0, s7, v0, 8

; SI-NEXT:    s_lshr_b32 s10, s7, 24

; SI-NEXT:    s_lshr_b32 s12, s7, 8

; SI-NEXT:    s_lshl_b64 s[8:9], s[6:7], 8

; SI-NEXT:    s_lshl_b64 s[32:33], s[6:7], 24

; SI-NEXT:    s_lshl_b32 s19, s6, 24

; SI-NEXT:    s_lshl_b32 s21, s6, 8

; SI-NEXT:    v_mov_b32_e32 v2, s4

; SI-NEXT:    v_alignbit_b32 v3, s5, v2, 24

; SI-NEXT:    v_alignbit_b32 v2, s5, v2, 8

; SI-NEXT:    s_lshr_b32 s32, s5, 8

; SI-NEXT:    s_lshl_b64 s[6:7], s[4:5], 8

; SI-NEXT:    s_and_b32 s15, s9, s25

; SI-NEXT:    s_lshl_b64 s[8:9], s[4:5], 24

; SI-NEXT:    s_lshl_b32 s29, s4, 24

; SI-NEXT:    s_lshl_b32 s4, s4, 8

; SI-NEXT:    v_mov_b32_e32 v0, s10

; SI-NEXT:    v_alignbit_b32 v1, s11, v0, 24

; SI-NEXT:    v_alignbit_b32 v0, s11, v0, 8

; SI-NEXT:    s_lshr_b32 s6, s11, 24

; SI-NEXT:    s_lshr_b32 s12, s11, 8

; SI-NEXT:    s_lshl_b64 s[4:5], s[10:11], 8

; SI-NEXT:    s_lshl_b64 s[32:33], s[10:11], 24

; SI-NEXT:    s_lshl_b32 s19, s10, 24

; SI-NEXT:    s_lshl_b32 s21, s10, 8

; SI-NEXT:    v_mov_b32_e32 v2, s8

; SI-NEXT:    v_alignbit_b32 v3, s9, v2, 24

; SI-NEXT:    v_alignbit_b32 v2, s9, v2, 8

; SI-NEXT:    s_lshr_b32 s32, s9, 8

; SI-NEXT:    s_lshl_b64 s[10:11], s[8:9], 8

; SI-NEXT:    s_and_b32 s15, s5, s25

; SI-NEXT:    s_lshl_b64 s[4:5], s[8:9], 24

; SI-NEXT:    s_lshl_b32 s29, s8, 24

; SI-NEXT:    s_lshl_b32 s4, s8, 8

; SI-NEXT:    v_and_b32_e32 v1, s31, v1

; SI-NEXT:    v_and_b32_e32 v0, s22, v0

; SI-NEXT:    s_and_b32 s12, s12, s27
@@ -377,28 +377,28 @@ define amdgpu_kernel void @test_bswap_v2i64(<2 x i64> addrspace(1)* %out, <2 x i 
; SI-NEXT:    v_and_b32_e32 v3, s31, v3

; SI-NEXT:    v_and_b32_e32 v2, s22, v2

; SI-NEXT:    s_and_b32 s22, s32, s27

; SI-NEXT:    s_and_b32 s25, s7, s25

; SI-NEXT:    s_and_b32 s27, s9, s27

; SI-NEXT:    s_and_b32 s25, s11, s25

; SI-NEXT:    s_and_b32 s27, s5, s27

; SI-NEXT:    s_and_b32 s31, s4, s31

; SI-NEXT:    v_or_b32_e32 v0, v0, v1

; SI-NEXT:    s_or_b64 s[6:7], s[12:13], s[10:11]

; SI-NEXT:    s_or_b64 s[8:9], s[16:17], s[14:15]

; SI-NEXT:    s_or_b64 s[4:5], s[12:13], s[6:7]

; SI-NEXT:    s_or_b64 s[10:11], s[16:17], s[14:15]

; SI-NEXT:    s_or_b64 s[12:13], s[18:19], s[20:21]

; SI-NEXT:    v_or_b32_e32 v1, v2, v3

; SI-NEXT:    s_lshr_b32 s10, s5, 24

; SI-NEXT:    s_or_b64 s[4:5], s[26:27], s[24:25]

; SI-NEXT:    s_lshr_b32 s6, s9, 24

; SI-NEXT:    s_or_b64 s[8:9], s[26:27], s[24:25]

; SI-NEXT:    s_or_b64 s[14:15], s[28:29], s[30:31]

; SI-NEXT:    v_or_b32_e32 v0, s6, v0

; SI-NEXT:    v_mov_b32_e32 v3, s7

; SI-NEXT:    s_or_b64 s[6:7], s[12:13], s[8:9]

; SI-NEXT:    s_or_b64 s[8:9], s[22:23], s[10:11]

; SI-NEXT:    s_or_b64 s[4:5], s[14:15], s[4:5]

; SI-NEXT:    v_or_b32_e32 v2, s6, v0

; SI-NEXT:    v_or_b32_e32 v3, s7, v3

; SI-NEXT:    v_or_b32_e32 v0, s8, v1

; SI-NEXT:    v_mov_b32_e32 v1, s9

; SI-NEXT:    v_or_b32_e32 v0, s4, v0

; SI-NEXT:    v_or_b32_e32 v1, s5, v1

; SI-NEXT:    v_mov_b32_e32 v3, s5

; SI-NEXT:    s_or_b64 s[4:5], s[12:13], s[10:11]

; SI-NEXT:    s_or_b64 s[6:7], s[22:23], s[6:7]

; SI-NEXT:    s_or_b64 s[8:9], s[14:15], s[8:9]

; SI-NEXT:    v_or_b32_e32 v2, s4, v0

; SI-NEXT:    v_or_b32_e32 v3, s5, v3

; SI-NEXT:    v_or_b32_e32 v0, s6, v1

; SI-NEXT:    v_mov_b32_e32 v1, s7

; SI-NEXT:    v_or_b32_e32 v0, s8, v0

; SI-NEXT:    v_or_b32_e32 v1, s9, v1

; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0

; SI-NEXT:    s_endpgm

;

llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll

+15 −15
Original line number Diff line number Diff line
@@ -314,26 +314,26 @@ define amdgpu_kernel void @test_copy_v4i8_extra_use(<4 x i8> addrspace(1)* %out0 
define amdgpu_kernel void @test_copy_v4i8_x2_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind {

; SI-LABEL: test_copy_v4i8_x2_extra_use:

; SI:       ; %bb.0:

; SI-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9

; SI-NEXT:    s_mov_b32 s11, 0xf000

; SI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x9

; SI-NEXT:    s_mov_b32 s3, 0xf000

; SI-NEXT:    s_mov_b32 s14, 0

; SI-NEXT:    s_mov_b32 s15, s11

; SI-NEXT:    s_mov_b32 s15, s3

; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0

; SI-NEXT:    s_waitcnt lgkmcnt(0)

; SI-NEXT:    s_mov_b64 s[12:13], s[6:7]

; SI-NEXT:    s_mov_b64 s[12:13], s[10:11]

; SI-NEXT:    v_mov_b32_e32 v1, 0

; SI-NEXT:    buffer_load_dword v0, v[0:1], s[12:15], 0 addr64

; SI-NEXT:    s_mov_b32 s16, 0xff00

; SI-NEXT:    s_movk_i32 s17, 0xff

; SI-NEXT:    s_mov_b32 s10, -1

; SI-NEXT:    s_mov_b32 s8, s4

; SI-NEXT:    s_mov_b32 s9, s5

; SI-NEXT:    s_mov_b32 s4, s2

; SI-NEXT:    s_mov_b32 s5, s3

; SI-NEXT:    s_mov_b32 s6, s10

; SI-NEXT:    s_mov_b32 s7, s11

; SI-NEXT:    s_mov_b32 s2, s10

; SI-NEXT:    s_mov_b32 s3, s11

; SI-NEXT:    s_mov_b32 s2, -1

; SI-NEXT:    s_mov_b32 s0, s8

; SI-NEXT:    s_mov_b32 s1, s9

; SI-NEXT:    s_mov_b32 s8, s6

; SI-NEXT:    s_mov_b32 s9, s7

; SI-NEXT:    s_mov_b32 s10, s2

; SI-NEXT:    s_mov_b32 s11, s3

; SI-NEXT:    s_mov_b32 s6, s2

; SI-NEXT:    s_mov_b32 s7, s3

; SI-NEXT:    s_waitcnt vmcnt(0)

; SI-NEXT:    v_add_i32_e32 v3, vcc, 9, v0

; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
@@ -349,9 +349,9 @@ define amdgpu_kernel void @test_copy_v4i8_x2_extra_use(<4 x i8> addrspace(1)* %o 
; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; SI-NEXT:    v_or_b32_e32 v1, v1, v2

; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x9000000, v1

; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0

; SI-NEXT:    buffer_store_dword v1, off, s[8:11], 0

; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0

; SI-NEXT:    buffer_store_dword v1, off, s[4:7], 0

; SI-NEXT:    buffer_store_dword v0, off, s[8:11], 0

; SI-NEXT:    s_endpgm

;

; VI-LABEL: test_copy_v4i8_x2_extra_use: