Commit 00852763 authored by Hans Wennborg's avatar Hans Wennborg
Browse files

Merging r323857: 

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r323857 | rogfer01 | 2018-01-31 10:23:43 +0100 (Wed, 31 Jan 2018) | 19 lines

[ARM] Allow the scheduler to clone a node with glue to avoid a copy CPSR ↔️ GPR.

In Thumb 1, with the new ADDCARRY / SUBCARRY the scheduler may need to do
copies CPSR ↔️ GPR but not all Thumb1 targets implement them.

The schedule can attempt, before attempting a copy, to clone the instructions
but it does not currently do that for nodes with input glue. In this patch we
introduce a target-hook to let the hook decide if a glued machinenode is still
eligible for copying. In this case these are ARM::tADCS and ARM::tSBCS .

As a follow-up of this change we should actually implement the copies for the
Thumb1 targets that do implement them and restrict the hook to the targets that
can't really do such copy as these clones are not ideal.

This change fixes PR35836.

Differential Revision: https://reviews.llvm.org/D42051


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llvm-svn: 324082
parent eeabe19e

llvm/include/llvm/CodeGen/TargetInstrInfo.h

+4 −0
Original line number Diff line number Diff line
@@ -950,6 +950,10 @@ public: 
  /// Return true when a target supports MachineCombiner.

  virtual bool useMachineCombiner() const { return false; }



  /// Return true if the given SDNode can be copied during scheduling

  /// even if it has glue.

  virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }



protected:

  /// Target-dependent implementation for foldMemoryOperand.

  /// Target-independent code in foldMemoryOperand will

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

+16 −4
Original line number Diff line number Diff line
@@ -1117,23 +1117,35 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { 
  if (!N)

    return nullptr;



  if (SU->getNode()->getGluedNode())

  DEBUG(dbgs() << "Considering duplicating the SU\n");

  DEBUG(SU->dump(this));



  if (N->getGluedNode() &&

      !TII->canCopyGluedNodeDuringSchedule(N)) {

    DEBUG(dbgs()

        << "Giving up because it has incoming glue and the target does not "

           "want to copy it\n");

    return nullptr;

  }



  SUnit *NewSU;

  bool TryUnfold = false;

  for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {

    MVT VT = N->getSimpleValueType(i);

    if (VT == MVT::Glue)

    if (VT == MVT::Glue) {

      DEBUG(dbgs() << "Giving up because it has outgoing glue\n");

      return nullptr;

    else if (VT == MVT::Other)

    } else if (VT == MVT::Other)

      TryUnfold = true;

  }

  for (const SDValue &Op : N->op_values()) {

    MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());

    if (VT == MVT::Glue)

    if (VT == MVT::Glue && !TII->canCopyGluedNodeDuringSchedule(N)) {

      DEBUG(dbgs() << "Giving up because it one of the operands is glue and "

                      "the target does not want to copy it\n");

      return nullptr;

    }

  }



  // If possible unfold instruction.

  if (TryUnfold) {

llvm/lib/Target/ARM/Thumb1InstrInfo.cpp

+13 −0
Original line number Diff line number Diff line
@@ -141,3 +141,16 @@ void Thumb1InstrInfo::expandLoadStackGuard( 
  else

    expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi);

}



bool Thumb1InstrInfo::canCopyGluedNodeDuringSchedule(SDNode *N) const {

  // In Thumb1 the scheduler may need to schedule a cross-copy between GPRS and CPSR

  // but this is not always possible there, so allow the Scheduler to clone tADCS and tSBCS

  // even if they have glue.

  // FIXME. Actually implement the cross-copy where it is possible (post v6)

  // because these copies entail more spilling.

  unsigned Opcode = N->getMachineOpcode();

  if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS)

    return true;



  return false;

}

llvm/lib/Target/ARM/Thumb1InstrInfo.h

+1 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ public: 
                            const TargetRegisterClass *RC,

                            const TargetRegisterInfo *TRI) const override;



  bool canCopyGluedNodeDuringSchedule(SDNode *N) const override;

private:

  void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;

};

llvm/test/CodeGen/Thumb/pr35836.ll

0 → 100644
+56 −0
Original line number Diff line number Diff line 
; RUN: llc < %s | FileCheck %s



target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"

target triple = "thumbv5e-none-linux-gnueabi"



; Function Attrs: norecurse nounwind optsize

define void @f(i32,i32,i32,i32,i32* %x4p, i32* %x5p, i32* %x6p) {

if.end:

  br label %while.body



while.body:

  %ll.0100 = phi i64 [ 0, %if.end ], [ %shr32, %while.body ]

  %add = add nuw nsw i64 %ll.0100, 0

  %add3 = add nuw nsw i64 %add, 0

  %shr = lshr i64 %add3, 32

  %conv7 = zext i32 %0 to i64

  %conv9 = zext i32 %1 to i64

  %add10 = add nuw nsw i64 %conv9, %conv7

  %add11 = add nuw nsw i64 %add10, %shr

  %shr14 = lshr i64 %add11, 32

  %conv16 = zext i32 %2 to i64

  %conv18 = zext i32 %3 to i64

  %add19 = add nuw nsw i64 %conv18, %conv16

  %add20 = add nuw nsw i64 %add19, %shr14

  %conv21 = trunc i64 %add20 to i32

  store i32 %conv21, i32* %x6p, align 4

  %shr23 = lshr i64 %add20, 32

  %x4 = load i32, i32* %x4p, align 4

  %conv25 = zext i32 %x4 to i64

  %x5 = load i32, i32* %x5p, align 4

  %conv27 = zext i32 %x5 to i64

  %add28 = add nuw nsw i64 %conv27, %conv25

  %add29 = add nuw nsw i64 %add28, %shr23

  %shr32 = lshr i64 %add29, 32

  br label %while.body

}

; CHECK: adds	r3, r0, r1

; CHECK: push	{r5}

; CHECK: pop	{r1}

; CHECK: adcs	r1, r1

; CHECK: ldr	r0, [sp, #12]           @ 4-byte Reload

; CHECK: ldr	r2, [sp, #8]            @ 4-byte Reload

; CHECK: adds	r2, r0, r2

; CHECK: push	{r5}

; CHECK: pop	{r4}

; CHECK: adcs	r4, r4

; CHECK: adds	r0, r2, r5

; CHECK: push	{r3}

; CHECK: pop	{r0}

; CHECK: adcs	r0, r4

; CHECK: ldr	r6, [sp, #4]            @ 4-byte Reload

; CHECK: str	r0, [r6]

; CHECK: ldr	r0, [r7]

; CHECK: ldr	r6, [sp]                @ 4-byte Reload

; CHECK: ldr	r6, [r6]

; CHECK: adds	r0, r6, r0