Unverified Commit 15335918 authored by Ayke van Laethem's avatar Ayke van Laethem
Browse files

[AVR] Remove regalloc workaround for LDDWRdPtrQ

Background: https://github.com/avr-rust/rust-legacy-fork/issues/126

In short, this workaround was introduced to fix a "ran out of registers
during regalloc" issue. The root cause has since been fixed in
https://reviews.llvm.org/D54218 so this workaround can be removed.

There is one test that changes a little bit, removing a single
instruction. I also compiled compiler-rt before and after this patch but
didn't see a difference. So presumably the impact is very low. Still,
it's nice to be able to remove such a workaround.

Differential Revision: https://reviews.llvm.org/D117831
parent eb3f20e8
...@@ -1394,7 +1394,7 @@ let canFoldAsLoad = 1, isReMaterializable = 1 in { ...@@ -1394,7 +1394,7 @@ let canFoldAsLoad = 1, isReMaterializable = 1 in {
// ldd Rd, P+q // ldd Rd, P+q
// ldd Rd+1, P+q+1 // ldd Rd+1, P+q+1
let Constraints = "@earlyclobber $dst" in def LDDWRdPtrQ let Constraints = "@earlyclobber $dst" in def LDDWRdPtrQ
: Pseudo<(outs DREGS_WITHOUT_YZ_WORKAROUND : Pseudo<(outs DREGS
: $dst), : $dst),
(ins memri (ins memri
: $memri), : $memri),
......
...@@ -178,26 +178,6 @@ def DREGSMOVW : RegisterClass<"AVR", [i16], 8, ...@@ -178,26 +178,6 @@ def DREGSMOVW : RegisterClass<"AVR", [i16], 8,
R29R28, R17R16, R15R14, R13R12, R11R10, R9R8, R29R28, R17R16, R15R14, R13R12, R11R10, R9R8,
R7R6, R5R4, R3R2, R1R0)>; R7R6, R5R4, R3R2, R1R0)>;
// The 16-bit DREGS register class, excluding the Z pointer register.
//
// This is used by instructions which cause high pointer register
// contention which leads to an assertion in the register allocator.
//
// There is no technical reason why instructions that use this class
// cannot use Z; it's simply a workaround a regalloc bug.
//
// More information can be found in PR39553.
def DREGS_WITHOUT_YZ_WORKAROUND
: RegisterClass<"AVR", [i16], 8,
(
// Return value and arguments.
add R25R24, R19R18, R21R20, R23R22,
// Scratch registers.
R27R26,
// Callee saved registers.
R17R16, R15R14, R13R12, R11R10, R9R8, R7R6, R5R4, R3R2,
R1R0)>;
// 16-bit register class for immediate instructions. // 16-bit register class for immediate instructions.
def DLDREGS : RegisterClass<"AVR", [i16], 8, def DLDREGS : RegisterClass<"AVR", [i16], 8,
( (
......
...@@ -22,13 +22,12 @@ define i16 @foo0(i16 %a) addrspace(1) { ...@@ -22,13 +22,12 @@ define i16 @foo0(i16 %a) addrspace(1) {
; CHECK-O0-NEXT: out 61, r28 ; CHECK-O0-NEXT: out 61, r28
; CHECK-O0-NEXT: std Y+1, r24 ; CHECK-O0-NEXT: std Y+1, r24
; CHECK-O0-NEXT: std Y+2, r25 ; CHECK-O0-NEXT: std Y+2, r25
; CHECK-O0-NEXT: ldd r24, Y+1 ; CHECK-O0-NEXT: ldd r30, Y+1
; CHECK-O0-NEXT: ldd r25, Y+2 ; CHECK-O0-NEXT: ldd r31, Y+2
; CHECK-O0-NEXT: lsl r24 ; CHECK-O0-NEXT: lsl r30
; CHECK-O0-NEXT: rol r25 ; CHECK-O0-NEXT: rol r31
; CHECK-O0-NEXT: subi r24, -lo8(arr0) ; CHECK-O0-NEXT: subi r30, -lo8(arr0)
; CHECK-O0-NEXT: sbci r25, -hi8(arr0) ; CHECK-O0-NEXT: sbci r31, -hi8(arr0)
; CHECK-O0-NEXT: movw r30, r24
; CHECK-O0-NEXT: lpm r24, Z+ ; CHECK-O0-NEXT: lpm r24, Z+
; CHECK-O0-NEXT: lpm r25, Z ; CHECK-O0-NEXT: lpm r25, Z
; CHECK-O0-NEXT: adiw r28, 2 ; CHECK-O0-NEXT: adiw r28, 2
...@@ -95,11 +94,10 @@ define i8 @foo1(i16 %a) addrspace(1) { ...@@ -95,11 +94,10 @@ define i8 @foo1(i16 %a) addrspace(1) {
; CHECK-O0-NEXT: out 61, r28 ; CHECK-O0-NEXT: out 61, r28
; CHECK-O0-NEXT: std Y+1, r24 ; CHECK-O0-NEXT: std Y+1, r24
; CHECK-O0-NEXT: std Y+2, r25 ; CHECK-O0-NEXT: std Y+2, r25
; CHECK-O0-NEXT: ldd r24, Y+1 ; CHECK-O0-NEXT: ldd r30, Y+1
; CHECK-O0-NEXT: ldd r25, Y+2 ; CHECK-O0-NEXT: ldd r31, Y+2
; CHECK-O0-NEXT: subi r24, -lo8(arr1) ; CHECK-O0-NEXT: subi r30, -lo8(arr1)
; CHECK-O0-NEXT: sbci r25, -hi8(arr1) ; CHECK-O0-NEXT: sbci r31, -hi8(arr1)
; CHECK-O0-NEXT: movw r30, r24
; CHECK-O0-NEXT: lpm r24, Z ; CHECK-O0-NEXT: lpm r24, Z
; CHECK-O0-NEXT: adiw r28, 2 ; CHECK-O0-NEXT: adiw r28, 2
; CHECK-O0-NEXT: in r0, 63 ; CHECK-O0-NEXT: in r0, 63
......
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