Unverified Commit 116ab786 authored by Ayke van Laethem's avatar Ayke van Laethem
Browse files

[AVR] Make use of the constant value 0 in R1

The register R1 is defined to have the constant value 0 in the avr-gcc
calling convention (which we follow). Unfortunately, we don't really
make use of it. This patch replaces `LDI 0` instructions with a copy
from R1.

This reduces code size: my AVR build of compiler-rt goes from 50660 to
50240 bytes of code size, which is a 0.8% reduction. Presumably it will
also improve execution speed, although I didn't measure this.

Differential Revision: https://reviews.llvm.org/D117425
parent 15335918
......@@ -1695,6 +1695,18 @@ MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
return BB;
}
// Insert a read from R1, which almost always contains the value 0.
MachineBasicBlock *
AVRTargetLowering::insertCopyR1(MachineInstr &MI, MachineBasicBlock *BB) const {
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
MachineBasicBlock::iterator I(MI);
BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::COPY))
.add(MI.getOperand(0))
.addReg(AVR::R1);
MI.eraseFromParent();
return BB;
}
MachineBasicBlock *
AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *MBB) const {
......@@ -1717,6 +1729,8 @@ AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case AVR::MULRdRr:
case AVR::MULSRdRr:
return insertMul(MI, MBB);
case AVR::CopyR1:
return insertCopyR1(MI, MBB);
}
assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
......
......@@ -187,6 +187,8 @@ protected:
private:
MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB) const;
MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const;
MachineBasicBlock *insertCopyR1(MachineInstr &MI,
MachineBasicBlock *BB) const;
};
} // end namespace llvm
......
......@@ -2390,6 +2390,10 @@ def Asr16 : ShiftPseudo<(outs DREGS
: $src, i8
: $cnt))]>;
// lowered to a copy from R1, which contains the value zero.
let usesCustomInserter=1 in
def CopyR1 : Pseudo<(outs GPR8:$rd), (ins), "clrz\t$rd", [(set i8:$rd, 0)]>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//
......
......@@ -18,7 +18,7 @@ entry-block:
; CHECK: ldi [[RET:r[0-9]+]], 1
; CHECK: cp {{.*}}[[HIGH]], {{.*}}[[LOW]]
; CHECK: brne [[LABEL:.LBB[_0-9]+]]
; CHECK: ldi {{.*}}[[RET]], 0
; CHECK: mov {{.*}}[[RET]], r1
; CHECK: {{.*}}[[LABEL]]
; CHECK: ret
}
......
......@@ -6,8 +6,7 @@
; CHECK-LABEL: foo
define void @foo() {
; CHECK: ldi [[SRC:r[0-9]+]], 0
; CHECK-NEXT: st [[PTRREG:X|Y|Z]], [[SRC]]
; CHECK: st [[PTRREG:X|Y|Z]], r1
store i8 0, i8* undef, align 4
ret void
}
......@@ -14,7 +14,7 @@ entry-block:
; CHECK: ldi [[RET:r[0-9]+]], 1
; CHECK: cpi {{.*}}[[HIGH]], 0
; CHECK: brne [[LABEL:.LBB[_0-9]+]]
; CHECK: ldi {{.*}}[[RET]], 0
; CHECK: mov {{.*}}[[RET]], r1
; CHECK: {{.*}}[[LABEL]]
; CHECK: ret
}
......
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