Commit dc24f83d authored by dill Upstream's avatar dill Upstream Committed by Eisenhauer, Greg
Browse files

dill 2019-12-12 (dac6dfcc) 

Code extracted from:

    https://github.com/GTkorvo/dill.git

at commit dac6dfcc7fdaceeb4c157f9ecdf5ecc28f20477f (master).

Upstream Shortlog
-----------------
parent e653548c

CMakeLists.txt

+4 −1
Original line number Diff line number Diff line 
cmake_minimum_required(VERSION 3.0)



project(DILL VERSION 2.4.0 LANGUAGES C CXX)

project(DILL VERSION 2.4.1 LANGUAGES C CXX)



# Some boilerplate to setup nice output directories

include(GNUInstallDirs)
@@ -265,6 +265,9 @@ check_include_files(unistd.h HAVE_UNISTD_H) 
check_include_files(stdarg.h STDC_HEADERS)

check_include_files(malloc.h HAVE_MALLOC_H)

check_include_files(memory.h HAVE_MEMORY_H)

include(CheckSymbolExists)

check_symbol_exists(__clear_cache "" CLEAR_CACHE_DEFINED)

message(STATUS "Clear cache defined is ${CLEAR_CACHE_DEFINED}")



set(NO_DISASSEMBLER TRUE)

if(DILL_ENABLE_DISASSEMBLY)

LICENSE

0 → 100644
+24 −0
Original line number Diff line number Diff line 
Copyright (c) 2010, Georgia Tech Research Corporation

All rights reserved.



Redistribution and use in source and binary forms, with or without

modification, are permitted provided that the following conditions are met:

    * Redistributions of source code must retain the above copyright

      notice, this list of conditions and the following disclaimer.

    * Redistributions in binary form must reproduce the above copyright

      notice, this list of conditions and the following disclaimer in the

      documentation and/or other materials provided with the distribution.

    * Neither the name of the Georgia Tech Research Corporation nor the

      names of its contributors may be used to endorse or promote products

      derived from this software without specific prior written permission.



THIS SOFTWARE IS PROVIDED BY GEORGIA TECH RESEARCH CORPORATION ''AS IS'' AND

ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

DISCLAIMED. IN NO EVENT SHALL GEORGIA TECH BE LIABLE FOR ANY DIRECT, INDIRECT,

INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,

OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF

LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE

OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

arm6.c

+3 −16
Original line number Diff line number Diff line
@@ -1526,22 +1526,9 @@ arm6_call_link(dill_stream s) 
}





/* Clear the instruction cache from `beg' to `end'.  This makes an

   inline system call to SYS_cacheflush.  */

#define CLEAR_INSN_CACHE(BEG, END)                                      \

{                                                                       \

  register unsigned long _beg __asm ("a1") = (unsigned long) (BEG);     \

  register unsigned long _end __asm ("a2") = (unsigned long) (END);     \

  register unsigned long _flg __asm ("a3") = 0;                         \

  __asm __volatile ("swi 0x9f0002               @ sys_cacheflush"       \

                    : "=r" (_beg)                                       \

                    : "0" (_beg), "r" (_end), "r" (_flg));              \

}

/*

 *  Cache flush code grabbed from a Dec 1999 posting on libc-hacker 

 *  mailing list

 */

extern void __clear_cache(char*, char *);

#ifndef CLEAR_CACHE_DEFINED

extern void __clear_cache(void *, void *);

#endif



static void

arm6_flush(void *base, void *limit)

arm6_rt.c

+3 −16
Original line number Diff line number Diff line
@@ -109,22 +109,9 @@ arm6_rt_call_link(char *code, call_t *t) 
    }

}



/* Clear the instruction cache from `beg' to `end'.  This makes an

   inline system call to SYS_cacheflush.  */

#define CLEAR_INSN_CACHE(BEG, END)                                      \

{                                                                       \

  register unsigned long _beg __asm ("a1") = (unsigned long) (BEG);     \

  register unsigned long _end __asm ("a2") = (unsigned long) (END);     \

  register unsigned long _flg __asm ("a3") = 0;                         \

  __asm __volatile ("swi 0x9f0002               @ sys_cacheflush"       \

                    : "=r" (_beg)                                       \

                    : "0" (_beg), "r" (_end), "r" (_flg));              \

}

/*

 *  Cache flush code grabbed from a Dec 1999 posting on libc-hacker 

 *  mailing list

 */

extern void __clear_cache(char*, char *);

#ifndef CLEAR_CACHE_DEFINED

extern void __clear_cache(void *, void *);

#endif



static void

arm6_flush(void *base, void *limit)

arm8.c

+3 −16
Original line number Diff line number Diff line
@@ -1524,22 +1524,9 @@ arm8_call_link(dill_stream s) 
}





/* Clear the instruction cache from `beg' to `end'.  This makes an

   inline system call to SYS_cacheflush.  */

#define CLEAR_INSN_CACHE(BEG, END)                                      \

{                                                                       \

  register unsigned long _beg __asm ("a1") = (unsigned long) (BEG);     \

  register unsigned long _end __asm ("a2") = (unsigned long) (END);     \

  register unsigned long _flg __asm ("a3") = 0;                         \

  __asm __volatile ("swi 0x9f0002               @ sys_cacheflush"       \

                    : "=r" (_beg)                                       \

                    : "0" (_beg), "r" (_end), "r" (_flg));              \

}

/*

 *  Cache flush code grabbed from a Dec 1999 posting on libc-hacker 

 *  mailing list

 */

extern void __clear_cache(char*, char *);

#ifndef CLEAR_CACHE_DEFINED

extern void __clear_cache(void *, void *);

#endif



static void

arm8_flush(void *base, void *limit)