Commit d0fb34dc authored by QingShan Zhang's avatar QingShan Zhang
Browse files

[PowerPC] Replace the PPCISD:: SExtVElems with ISD::SIGN_EXTEND_INREG to leverage the combine rules 

The PPCISD::SExtVElems was added by commit https://reviews.llvm.org/D34009. However,
we have another ISD node ISD::SIGN_EXTEND_INREG that perfectly match the semantics
of SExtVElems. And the DAGCombiner has some combine rules for SIGN_EXTEND_INREG
that produce better code.

Differential Revision: https://reviews.llvm.org/D70771
parent 09c8f389

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

+18 −11
Original line number Diff line number Diff line
@@ -1430,7 +1430,6 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 
  case PPCISD::LXSIZX:          return "PPCISD::LXSIZX";

  case PPCISD::STXSIX:          return "PPCISD::STXSIX";

  case PPCISD::VEXTS:           return "PPCISD::VEXTS";

  case PPCISD::SExtVElems:      return "PPCISD::SExtVElems";

  case PPCISD::LXVD2X:          return "PPCISD::LXVD2X";

  case PPCISD::STXVD2X:         return "PPCISD::STXVD2X";

  case PPCISD::LOAD_VEC_BE:     return "PPCISD::LOAD_VEC_BE";
@@ -8051,16 +8050,19 @@ SDValue PPCTargetLowering::LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG, 
  SDValue ShuffleSrc2 =

      SignedConv ? DAG.getUNDEF(WideVT) : DAG.getConstant(0, dl, WideVT);

  SDValue Arrange = DAG.getVectorShuffle(WideVT, dl, Wide, ShuffleSrc2, ShuffV);

  unsigned ExtendOp =

      SignedConv ? (unsigned)PPCISD::SExtVElems : (unsigned)ISD::BITCAST;















  SDValue Extend;













  if (!Subtarget.hasP9Altivec() && SignedConv) {













  if (SignedConv) {















    Arrange = DAG.getBitcast(IntermediateVT, Arrange);













    EVT ExtVT = Op.getOperand(0).getValueType();













    if (Subtarget.hasP9Altivec())













      ExtVT = EVT::getVectorVT(*DAG.getContext(), WideVT.getVectorElementType(),













                               IntermediateVT.getVectorNumElements());



























    Extend = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, IntermediateVT, Arrange,













                         DAG.getValueType(Op.getOperand(0).getValueType()));













                         DAG.getValueType(ExtVT));















  } else













    Extend = DAG.getNode(ExtendOp, dl, IntermediateVT, Arrange);













    Extend = DAG.getNode(ISD::BITCAST, dl, IntermediateVT, Arrange);





























  return DAG.getNode(Opc, dl, Op.getValueType(), Extend);















}










@@ -13171,15 +13173,20 @@ static SDValue addShuffleForVecExtend(SDNode *N, SelectionDAG &DAG,













      DAG.getVectorShuffle(Input.getValueType(), dl, Input,















                           DAG.getUNDEF(Input.getValueType()), ShuffleMask);



























  EVT Ty = N->getValueType(0);













  SDValue BV = DAG.getNode(PPCISD::SExtVElems, dl, Ty, Shuffle);













  return BV;













  EVT VT = N->getValueType(0);













  SDValue Conv = DAG.getBitcast(VT, Shuffle);

























  EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),













                               Input.getValueType().getVectorElementType(),













                               VT.getVectorNumElements());













  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Conv,













                     DAG.getValueType(ExtVT));















}





























// Look for build vector patterns where input operands come from sign















// extended vector_extract elements of specific indices. If the correct indices













// aren't used, add a vector shuffle to fix up the indices and create a new













// PPCISD:SExtVElems node which selects the vector sign extend instructions













// aren't used, add a vector shuffle to fix up the indices and create













// SIGN_EXTEND_INREG node which selects the vector sign extend instructions















// during instruction selection.















static SDValue combineBVOfVecSExt(SDNode *N, SelectionDAG &DAG) {















  // This array encodes the indices that the vector sign extend instructions

























llvm/lib/Target/PowerPC/PPCISelLowering.h



+0
−4






























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@@ -85,10 +85,6 @@ namespace llvm {













    /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.















    VEXTS,





























    /// SExtVElems, takes an input vector of a smaller type and sign













    /// extends to an output vector of a larger type.













    SExtVElems,





























    /// Reciprocal estimate instructions (unary FP ops).















    FRE,















    FRSQRTE,

































llvm/lib/Target/PowerPC/PPCInstrInfo.td



+0
−4






























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@@ -37,9 +37,6 @@ def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [













def SDT_PPCVexts  : SDTypeProfile<1, 2, [















  SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2>















]>;













def SDT_PPCSExtVElems  : SDTypeProfile<1, 1, [













  SDTCisVec<0>, SDTCisVec<1>













]>;































def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,















                                           SDTCisVT<1, i32> ]>;










@@ -151,7 +148,6 @@ def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx,













def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix,















                       [SDNPHasChain, SDNPMayStore]>;















def PPCVexts  : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>;













def PPCSExtVElems  : SDNode<"PPCISD::SExtVElems", SDT_PPCSExtVElems, []>;































// Extract FPSCR (not modeled at the DAG level).















def PPCmffs   : SDNode<"PPCISD::MFFS",

































llvm/lib/Target/PowerPC/PPCInstrVSX.td



+0
−13






























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@@ -4397,19 +4397,6 @@ let AddedComplexity = 400 in {













    def : Pat<(v2i64 (build_vector ByteToDWord.BE_A0, ByteToDWord.BE_A1)),















              (v2i64 (VEXTSB2D $A))>;















  }



























  let Predicates = [HasP9Altivec] in {













    def: Pat<(v2i64 (PPCSExtVElems v16i8:$A)),













              (v2i64 (VEXTSB2D $A))>;













    def: Pat<(v2i64 (PPCSExtVElems v8i16:$A)),













              (v2i64 (VEXTSH2D $A))>;













    def: Pat<(v2i64 (PPCSExtVElems v4i32:$A)),













              (v2i64 (VEXTSW2D $A))>;













    def: Pat<(v4i32 (PPCSExtVElems v16i8:$A)),













              (v4i32 (VEXTSB2W $A))>;













    def: Pat<(v4i32 (PPCSExtVElems v8i16:$A)),













              (v4i32 (VEXTSH2W $A))>;













  }















}































// Put this P9Altivec related definition here since it's possible to be