Commit cfe2fab7 authored by Sanjay Patel's avatar Sanjay Patel
Browse files

[InstSimplify] add tests for vector select; NFC

parent e3ed63e8

llvm/test/Transforms/InstCombine/select.ll

+9 −9
Original line number Diff line number Diff line
@@ -1572,17 +1572,17 @@ define float @copysign3(float %x) { 
  ret float %r

}



define float @copysign4(float %x) {

define <2 x float> @copysign4(<2 x float> %x) {

; CHECK-LABEL: @copysign4(

; CHECK-NEXT:    [[I:%.*]] = bitcast float [[X:%.*]] to i32

; CHECK-NEXT:    [[ISNEG:%.*]] = icmp slt i32 [[I]], 0

; CHECK-NEXT:    [[R:%.*]] = select nnan arcp i1 [[ISNEG]], float -4.400000e+01, float 4.400000e+01

; CHECK-NEXT:    ret float [[R]]

; CHECK-NEXT:    [[I:%.*]] = bitcast <2 x float> [[X:%.*]] to <2 x i32>

; CHECK-NEXT:    [[ISNEG:%.*]] = icmp slt <2 x i32> [[I]], zeroinitializer

; CHECK-NEXT:    [[R:%.*]] = select nnan arcp <2 x i1> [[ISNEG]], <2 x float> <float 4.200000e+01, float undef>, <2 x float> <float -4.200000e+01, float -4.200000e+01>

; CHECK-NEXT:    ret <2 x float> [[R]]

;

  %i = bitcast float %x to i32

  %isneg = icmp ugt i32 %i, 2147483647

  %r = select arcp nnan i1 %isneg, float -44.0, float 44.0

  ret float %r

  %i = bitcast <2 x float> %x to <2 x i32>

  %isneg = icmp ugt <2 x i32> %i, <i32 2147483647, i32 2147483647>

  %r = select arcp nnan <2 x i1> %isneg, <2 x float> <float 42.0, float undef>, <2 x float> <float -42.0, float -42.0>

  ret <2 x float> %r

}



declare void @use1(i1)

llvm/test/Transforms/InstSimplify/select.ll

+20 −3
Original line number Diff line number Diff line
@@ -41,14 +41,31 @@ define i32 @cond_is_true(i32 %A, i32 %B) { 
  ret i32 %C

}



define i32 @equal_arms(i1 %C, i32 %I) {

define i32 @equal_arms(i1 %cond, i32 %x) {

; CHECK-LABEL: @equal_arms(

; CHECK-NEXT:    ret i32 [[I:%.*]]

; CHECK-NEXT:    ret i32 [[X:%.*]]

;

  %V = select i1 %C, i32 %I, i32 %I

  %V = select i1 %cond, i32 %x, i32 %x

  ret i32 %V

}



define <2 x i32> @equal_arms_vec(<2 x i1> %cond, <2 x i32> %x) {

; CHECK-LABEL: @equal_arms_vec(

; CHECK-NEXT:    ret <2 x i32> [[X:%.*]]

;

  %V = select <2 x i1> %cond, <2 x i32> %x, <2 x i32> %x

  ret <2 x i32> %V

}



define <2 x i32> @equal_arms_vec_undef(<2 x i1> %cond) {

; CHECK-LABEL: @equal_arms_vec_undef(

; CHECK-NEXT:    [[V:%.*]] = select <2 x i1> [[COND:%.*]], <2 x i32> <i32 42, i32 undef>, <2 x i32> <i32 undef, i32 42>

; CHECK-NEXT:    ret <2 x i32> [[V]]

;

  %V = select <2 x i1> %cond, <2 x i32> <i32 42, i32 undef>, <2 x i32> <i32 undef, i32 42>

  ret <2 x i32> %V

}



define <2 x i8> @vsel_tvec(<2 x i8> %x, <2 x i8> %y) {

; CHECK-LABEL: @vsel_tvec(

; CHECK-NEXT:    ret <2 x i8> [[X:%.*]]