Commit c36763d8 authored by Craig Topper's avatar Craig Topper
Browse files

[X86] Call SimplifyMultipleUseDemandedBits from combineVSelectToBLENDV if the... 

[X86] Call SimplifyMultipleUseDemandedBits from combineVSelectToBLENDV if the condition is used by something other than select conditions.

We might be able to bypass some nodes on the condition path.

Differential Revision: https://reviews.llvm.org/D71984
parent d8117542

llvm/lib/Target/X86/X86ISelLowering.cpp

+42 −24
Original line number Diff line number Diff line
@@ -37602,14 +37602,18 @@ static SDValue combineVSelectToBLENDV(SDNode *N, SelectionDAG &DAG, 
  if (VT.is512BitVector())

    return SDValue();













  // TODO: Add other opcodes eventually lowered into BLEND.













  auto OnlyUsedAsSelectCond = [](SDValue Cond) {















    for (SDNode::use_iterator UI = Cond->use_begin(), UE = Cond->use_end();















         UI != UE; ++UI)















      if ((UI->getOpcode() != ISD::VSELECT &&















           UI->getOpcode() != X86ISD::BLENDV) ||















          UI.getOperandNo() != 0)













      return SDValue();













        return false;



























    return true;













  };

























  if (OnlyUsedAsSelectCond(Cond)) {















    APInt DemandedMask(APInt::getSignMask(BitWidth));















    KnownBits Known;















    TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),









@@ -37635,6 +37639,20 @@ static SDValue combineVSelectToBLENDV(SDNode *N, SelectionDAG &DAG,













    return SDValue(N, 0);















  }



























  // Otherwise we can still at least try to simplify multiple use bits.













  APInt DemandedMask(APInt::getSignMask(BitWidth));













  APInt DemandedElts(APInt::getAllOnesValue(VT.getVectorNumElements()));













  KnownBits Known;













  TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),













                                        !DCI.isBeforeLegalizeOps());













  if (SDValue V = TLI.SimplifyMultipleUseDemandedBits(Cond, DemandedMask,













                                                      DemandedElts, DAG, 0))













    return DAG.getNode(X86ISD::BLENDV, SDLoc(N), N->getValueType(0),













                       V, N->getOperand(1), N->getOperand(2));

























  return SDValue();













}



























/// Do target-specific dag combines on SELECT and VSELECT nodes.















static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,















                             TargetLowering::DAGCombinerInfo &DCI,

























llvm/test/CodeGen/X86/vselect.ll



+3
−3






























Original line number
Diff line number
Diff line








@@ -536,17 +536,17 @@ define <2 x i64> @shrunkblend_nonvselectuse(<2 x i1> %cond, <2 x i64> %a, <2 x i













; SSE41:       # %bb.0:















; SSE41-NEXT:    psllq $63, %xmm0















; SSE41-NEXT:    psrad $31, %xmm0













; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]















; SSE41-NEXT:    blendvpd %xmm0, %xmm1, %xmm2













; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]















; SSE41-NEXT:    paddq %xmm2, %xmm0















; SSE41-NEXT:    retq















;















; AVX-LABEL: shrunkblend_nonvselectuse:















; AVX:       # %bb.0:















; AVX-NEXT:    vpsllq $63, %xmm0, %xmm0













; AVX-NEXT:    vpxor %xmm3, %xmm3, %xmm3













; AVX-NEXT:    vpcmpgtq %xmm0, %xmm3, %xmm0















; AVX-NEXT:    vblendvpd %xmm0, %xmm1, %xmm2, %xmm1













; AVX-NEXT:    vxorpd %xmm2, %xmm2, %xmm2













; AVX-NEXT:    vpcmpgtq %xmm0, %xmm2, %xmm0















; AVX-NEXT:    vpaddq %xmm0, %xmm1, %xmm0















; AVX-NEXT:    retq















  %x = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b