Commit a5376f63 authored by Craig Topper's avatar Craig Topper
Browse files

[GlobalISel][AArch64][AMDGPU][X86] Teach LegalizationArtifactCombiner to combine trunc(g_constant). 

This allows X86 to properly form shift by immediate instructions
since we require an 8-bit constant to match the imported
SelectionDAG patterns.
parent 76ee21e1

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

+29 −0
Original line number Diff line number Diff line
@@ -157,6 +157,32 @@ public: 
    return tryFoldImplicitDef(MI, DeadInsts);

  }



  bool tryCombineTrunc(MachineInstr &MI,

                       SmallVectorImpl<MachineInstr *> &DeadInsts) {

    assert(MI.getOpcode() == TargetOpcode::G_TRUNC);



    Builder.setInstr(MI);

    Register DstReg = MI.getOperand(0).getReg();

    Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());



    // Try to fold trunc(g_constant) when the smaller constant type is legal.

    // Can't use MIPattern because we don't have a specific constant in mind.

    auto *SrcMI = MRI.getVRegDef(SrcReg);

    if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) {

      const LLT &DstTy = MRI.getType(DstReg);

      if (isInstLegal({TargetOpcode::G_CONSTANT, {DstTy}})) {

        auto &CstVal = SrcMI->getOperand(1);

        Builder.buildConstant(

            DstReg, CstVal.getCImm()->getValue().trunc(DstTy.getSizeInBits()));

        markInstAndDefDead(MI, *SrcMI, DeadInsts);

        return true;

      }

    }



    return false;

  }





  /// Try to fold G_[ASZ]EXT (G_IMPLICIT_DEF).

  bool tryFoldImplicitDef(MachineInstr &MI,

                          SmallVectorImpl<MachineInstr *> &DeadInsts) {
@@ -420,6 +446,9 @@ public: 
    case TargetOpcode::G_EXTRACT:

      return tryCombineExtract(MI, DeadInsts);

    case TargetOpcode::G_TRUNC: {

      if (tryCombineTrunc(MI, DeadInsts))

        return true;



      bool Changed = false;

      for (auto &Use : MRI.use_instructions(MI.getOperand(0).getReg()))

        Changed |= tryCombineInstruction(Use, DeadInsts, WrapperObserver);

llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir

+12 −13
Original line number Diff line number Diff line
@@ -6,19 +6,18 @@ name: test_merge_s4 
body: |

  bb.0:

    ; CHECK-LABEL: name: test_merge_s4

    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0

    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4

    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 15

    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)

    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C2]]

    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)

    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)

    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C2]]

    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)

    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[COPY]]

    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR]](s32)

    ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)

    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s8)

    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4

    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15

    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[C2]], [[C1]]

    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)

    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32)

    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]

    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)

    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[COPY1]]

    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[OR]](s32)

    ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[TRUNC]](s8)

    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY2]](s8)

    ; CHECK: $x0 = COPY [[ANYEXT]](s64)

    %0:_(s64) = G_CONSTANT i64 0

    %1:_(s4) = G_TRUNC %0

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir

+4 −5
Original line number Diff line number Diff line
@@ -10,11 +10,10 @@ body: | 
    ; CHECK-LABEL: name: test_sext_trunc_i64_i32_i64

    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1

    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)

    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32

    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)

    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[TRUNC]](s32)

    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)

    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[TRUNC1]](s32)

    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32

    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s32)

    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)

    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY2]](s32)

    ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)

    %0:_(s64) = COPY $vgpr0_vgpr1

    %1:_(s32) = G_TRUNC %0

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir

+8 −10
Original line number Diff line number Diff line
@@ -804,11 +804,10 @@ body: | 
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: test_extract_s8_s64_offset2

    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1

    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2

    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)

    ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)

    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)

    ; CHECK: $vgpr0 = COPY [[TRUNC1]](s32)

    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2

    ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s32)

    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)

    ; CHECK: $vgpr0 = COPY [[TRUNC]](s32)

    %0:_(s64) = COPY $vgpr0_vgpr1

    %1:_(s8) = G_EXTRACT %0, 2

    %2:_(s32) = G_ANYEXT %1
@@ -841,11 +840,10 @@ body: | 
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: test_extract_s8_s64_offset16

    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1

    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16

    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)

    ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)

    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)

    ; CHECK: $vgpr0 = COPY [[TRUNC1]](s32)

    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16

    ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s32)

    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)

    ; CHECK: $vgpr0 = COPY [[TRUNC]](s32)

    %0:_(s64) = COPY $vgpr0_vgpr1

    %1:_(s8) = G_EXTRACT %0, 16

    %2:_(s32) = G_ANYEXT %1

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir

+42 −54
Original line number Diff line number Diff line
@@ -141,10 +141,9 @@ body: | 
    ; SI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808

    ; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807

    ; SI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]

    ; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32

    ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)

    ; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)

    ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[TRUNC]](s32)

    ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32

    ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C2]](s32)

    ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]

    ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]]

    ; SI: $vgpr0_vgpr1 = COPY [[OR]](s64)
@@ -154,10 +153,9 @@ body: | 
    ; VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808

    ; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807

    ; VI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]

    ; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32

    ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)

    ; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)

    ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[TRUNC]](s32)

    ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32

    ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C2]](s32)

    ; VI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]

    ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]]

    ; VI: $vgpr0_vgpr1 = COPY [[OR]](s64)
@@ -167,10 +165,9 @@ body: | 
    ; GFX9: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808

    ; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807

    ; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]

    ; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32

    ; GFX9: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)

    ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)

    ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[TRUNC]](s32)

    ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32

    ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C2]](s32)

    ; GFX9: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]

    ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]]

    ; GFX9: $vgpr0_vgpr1 = COPY [[OR]](s64)
@@ -192,11 +189,10 @@ body: | 
    ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648

    ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647

    ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]

    ; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32

    ; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)

    ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC]](s32)

    ; SI: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)

    ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]

    ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32

    ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)

    ; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)

    ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]

    ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND1]]

    ; SI: $vgpr0 = COPY [[OR]](s32)

    ; VI-LABEL: name: test_copysign_s32_s64
@@ -205,11 +201,10 @@ body: | 
    ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648

    ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647

    ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]

    ; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32

    ; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)

    ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC]](s32)

    ; VI: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)

    ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]

    ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32

    ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)

    ; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)

    ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]

    ; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND1]]

    ; VI: $vgpr0 = COPY [[OR]](s32)

    ; GFX9-LABEL: name: test_copysign_s32_s64
@@ -218,11 +213,10 @@ body: | 
    ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648

    ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647

    ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]

    ; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32

    ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)

    ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC]](s32)

    ; GFX9: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)

    ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]

    ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32

    ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)

    ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)

    ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]

    ; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND1]]

    ; GFX9: $vgpr0 = COPY [[OR]](s32)

    %0:_(s32) = COPY $vgpr0
@@ -354,12 +348,11 @@ body: | 
    ; SI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808

    ; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807

    ; SI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]

    ; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48

    ; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535

    ; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535

    ; SI: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)

    ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C3]]

    ; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)

    ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[TRUNC]](s32)

    ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]]

    ; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48

    ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)

    ; SI: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]

    ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND2]]

    ; SI: $vgpr0_vgpr1 = COPY [[OR]](s64)
@@ -369,12 +362,11 @@ body: | 
    ; VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808

    ; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807

    ; VI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]

    ; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48

    ; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535

    ; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535

    ; VI: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)

    ; VI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C3]]

    ; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)

    ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[TRUNC]](s32)

    ; VI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]]

    ; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48

    ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)

    ; VI: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]

    ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND2]]

    ; VI: $vgpr0_vgpr1 = COPY [[OR]](s64)
@@ -384,12 +376,11 @@ body: | 
    ; GFX9: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808

    ; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807

    ; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]

    ; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48

    ; GFX9: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535

    ; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535

    ; GFX9: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)

    ; GFX9: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C3]]

    ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)

    ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[TRUNC]](s32)

    ; GFX9: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]]

    ; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48

    ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)

    ; GFX9: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]

    ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND2]]

    ; GFX9: $vgpr0_vgpr1 = COPY [[OR]](s64)
@@ -413,11 +404,10 @@ body: | 
    ; SI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768

    ; SI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767

    ; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]

    ; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48

    ; SI: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)

    ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC1]](s32)

    ; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)

    ; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]

    ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 48

    ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)

    ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)

    ; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]

    ; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]

    ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)

    ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
@@ -428,11 +418,10 @@ body: | 
    ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768

    ; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767

    ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]

    ; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48

    ; VI: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)

    ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC1]](s32)

    ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)

    ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]

    ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 48

    ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)

    ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)

    ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]

    ; VI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]

    ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)

    ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
@@ -443,11 +432,10 @@ body: | 
    ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768

    ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767

    ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]

    ; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48

    ; GFX9: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)

    ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC1]](s32)

    ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)

    ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]

    ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 48

    ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)

    ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)

    ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]

    ; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]

    ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)

    ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)