Commit 94a24e7a authored by Petar Avramovic's avatar Petar Avramovic
Browse files

[MIPS GlobalISel] Select bswap 

G_BSWAP is generated from llvm.bswap.<type> intrinsics, clang genrates
these intrinsics from __builtin_bswap32 and __builtin_bswap64.
Add lower and narrowscalar for G_BSWAP.
Lower G_BSWAP on MIPS32, select G_BSWAP on MIPS32 revision 2 and later.

Differential Revision: https://reviews.llvm.org/D71362
parent cd2a73a9

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

+1 −0
Original line number Diff line number Diff line
@@ -237,6 +237,7 @@ public: 
  LegalizeResult lowerExtract(MachineInstr &MI);

  LegalizeResult lowerInsert(MachineInstr &MI);

  LegalizeResult lowerSADDO_SSUBO(MachineInstr &MI);

  LegalizeResult lowerBswap(MachineInstr &MI);



private:

  MachineRegisterInfo &MRI;

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

+58 −0
Original line number Diff line number Diff line
@@ -1075,6 +1075,27 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, 
    MI.eraseFromParent();

    return Legalized;

  }

  case TargetOpcode::G_BSWAP: {

    if (SizeOp0 % NarrowSize != 0)

      return UnableToLegalize;



    Observer.changingInstr(MI);

    SmallVector<Register, 2> SrcRegs, DstRegs;

    unsigned NumParts = SizeOp0 / NarrowSize;

    extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);



    for (unsigned i = 0; i < NumParts; ++i) {

      auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},

                                           {SrcRegs[NumParts - 1 - i]});

      DstRegs.push_back(DstPart.getReg(0));

    }



    MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);



    Observer.changedInstr(MI);

    MI.eraseFromParent();

    return Legalized;

  }

  }

}
@@ -2289,6 +2310,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) { 
    return lowerExtract(MI);

  case G_INSERT:

    return lowerInsert(MI);

  case G_BSWAP:

    return lowerBswap(MI);

  }

}
@@ -4326,3 +4349,38 @@ LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) { 
  MI.eraseFromParent();

  return Legalized;

}



LegalizerHelper::LegalizeResult

LegalizerHelper::lowerBswap(MachineInstr &MI) {

  Register Dst = MI.getOperand(0).getReg();

  Register Src = MI.getOperand(1).getReg();

  const LLT Ty = MRI.getType(Src);

  unsigned SizeInBytes = Ty.getSizeInBytes();

  unsigned BaseShiftAmt = (SizeInBytes - 1) * 8;



  // Swap most and least significant byte, set remaining bytes in Res to zero.

  auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt);

  auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt);

  auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);

  auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft);



  // Set i-th high/low byte in Res to i-th low/high byte from Src.

  for (unsigned i = 1; i < SizeInBytes / 2; ++i) {

    // AND with Mask leaves byte i unchanged and sets remaining bytes to 0.

    APInt APMask(SizeInBytes * 8, 0xFF << (i * 8));

    auto Mask = MIRBuilder.buildConstant(Ty, APMask);

    auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i);

    // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt.

    auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask);

    auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt);

    Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft);

    // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask.

    auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);

    auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask);

    Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight);

  }

  Res.getInstr()->getOperand(0).setReg(Dst);



  MI.eraseFromParent();

  return Legalized;

}

llvm/lib/Target/Mips/MipsLegalizerInfo.cpp

+13 −0
Original line number Diff line number Diff line
@@ -185,6 +185,19 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { 
  getActionDefinitionsBuilder(G_VASTART)

     .legalFor({p0});



  getActionDefinitionsBuilder(G_BSWAP)

      .legalIf([=, &ST](const LegalityQuery &Query) {

        if (ST.hasMips32r2() && CheckTyN(0, Query, {s32}))

          return true;

        return false;

      })

      .lowerIf([=, &ST](const LegalityQuery &Query) {

        if (!ST.hasMips32r2() && CheckTyN(0, Query, {s32}))

          return true;

        return false;

      })

      .maxScalar(0, s32);



  // FP instructions

  getActionDefinitionsBuilder(G_FCONSTANT)

      .legalFor({s32, s64});

llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp

+1 −0
Original line number Diff line number Diff line
@@ -451,6 +451,7 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { 
  case G_LSHR:

  case G_BRINDIRECT:

  case G_VASTART:

  case G_BSWAP:

    OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];

    break;

  case G_ADD:

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir

0 → 100644
+30 −0
Original line number Diff line number Diff line 
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=instruction-select -mattr=+mips32r2 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R2

--- |



  define void @bswap_i32() { entry: ret void }



...

---

name:            bswap_i32

alignment:       4

legalized:       true

regBankSelected: true

tracksRegLiveness: true

body:             |

  bb.1.entry:

    liveins: $a0



    ; MIPS32R2-LABEL: name: bswap_i32

    ; MIPS32R2: liveins: $a0

    ; MIPS32R2: [[COPY:%[0-9]+]]:gpr32 = COPY $a0

    ; MIPS32R2: [[WSBH:%[0-9]+]]:gpr32 = WSBH [[COPY]]

    ; MIPS32R2: [[ROTR:%[0-9]+]]:gpr32 = ROTR [[WSBH]], 16

    ; MIPS32R2: $v0 = COPY [[ROTR]]

    ; MIPS32R2: RetRA implicit $v0

    %0:gprb(s32) = COPY $a0

    %1:gprb(s32) = G_BSWAP %0

    $v0 = COPY %1(s32)

    RetRA implicit $v0



...