Commit 555e7ee0 authored by Matt Arsenault's avatar Matt Arsenault Committed by Matt Arsenault
Browse files

AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs 

We don't use the xexec register classes for arbitrary values
anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
parent a10527cd

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

+1 −1
Original line number Diff line number Diff line
@@ -1784,7 +1784,7 @@ SIRegisterInfo::getRegClassForSizeOnBank(unsigned Size, 
                                                 &AMDGPU::SReg_32RegClass;

  case 64:

    return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_64RegClass :

                                                 &AMDGPU::SReg_64_XEXECRegClass;

                                                 &AMDGPU::SReg_64RegClass;

  case 96:

    return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_96RegClass :

                                                 &AMDGPU::SReg_96RegClass;

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir

+2 −2
Original line number Diff line number Diff line
@@ -97,14 +97,14 @@ body: | 
    liveins: $sgpr0_sgpr1, $vgpr0

    ; WAVE64-LABEL: name: class_s64_vcc_sv

    ; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0

    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1

    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]

    ; WAVE32-LABEL: name: class_s64_vcc_sv

    ; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0

    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1

    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir

+1 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ body: | 


    ; CHECK-LABEL: name: fract_s64_vs

    ; CHECK: liveins: $sgpr0_sgpr1

    ; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1

    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; CHECK: [[V_FRACT_F64_e64_:%[0-9]+]]:vreg_64 = V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F64_e64_]]

    %0:sgpr(s64) = COPY $sgpr0_sgpr1

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir

+1 −1
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ body: | 
    liveins: $sgpr0_sgpr1, $vgpr0

    ; GCN-LABEL: name: ldexp_s64_vsv

    ; GCN: liveins: $sgpr0_sgpr1, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1

    ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_LDEXP_F64_:%[0-9]+]]:vreg_64 = V_LDEXP_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F64_]]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir

+1 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ body: | 


    ; CHECK-LABEL: name: rcp_s64_vs

    ; CHECK: liveins: $sgpr0_sgpr1

    ; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1

    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; CHECK: [[V_RCP_F64_e64_:%[0-9]+]]:vreg_64 = V_RCP_F64_e64 0, [[COPY]], 0, 0, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_F64_e64_]]

    %0:sgpr(s64) = COPY $sgpr0_sgpr1