-DesignTarget: cache

-CacheAccessMode: Normal
-Associativity (for cache only): 1

-ProcessNode: 65

-Capacity (MB): 2
//-WordWidth (bit): 64
-WordWidth (bit): 256

-DeviceRoadmap: LOP

-LocalWireType: LocalAggressive
-LocalWireRepeaterType: RepeatedNone
-LocalWireUseLowSwing: No

-GlobalWireType: GlobalAggressive
-GlobalWireRepeaterType: RepeatedNone
-GlobalWireUseLowSwing: No

-Routing: H-tree
//-Routing: Non-H-tree

-InternalSensing: true

-MemoryCellInputFile: sample_SRAM.cell

-Temperature (K): 350

-OptimizationTarget: WriteEDP
//-OptimizationTarget: Full
//-OptimizationTarget: ReadLatency
//-OptimizationTarget: ReadDynamicEnergy
-EnablePruning: Yes

-BufferDesignOptimization: latency

//-ForceBank3D (Total AxBxC, Active DxE): 1x1x4, 1x1
//-ForceBank (Total AxB, Active CxD): 1x1, 1x1
//-ForceMat (Total AxB, Active CxD): 1x1, 1x1
//-ForceMuxSenseAmp: 128
//-ForceMuxOutputLev1: 1 
//-ForceMuxOutputLev2: 1

-StackedDieCount: 2
-PartitionGranularity: 0
-LocalTSVProjection: 0
-GlobalTSVProjection: 0
-TSVRedundancy: 1.0