-DesignTarget: cache
-CacheAccessMode: Normal
-Associativity (for cache only): 16

-ProcessNode: 32

-Capacity (MB): 32
-WordWidth (bit): 256

-DeviceRoadmap: HP

-LocalWireType: LocalAggressive
-LocalWireRepeaterType: RepeatedNone
-LocalWireUseLowSwing: No

-GlobalWireType: GlobalAggressive
-GlobalWireRepeaterType: RepeatedNone
-GlobalWireUseLowSwing: No

-Routing: H-tree
//-Routing: Non-H-tree

-InternalSensing: true

-MemoryCellInputFile: sample_PCRAM.cell

-Temperature (K): 350

-EnablePruning: Yes
//-OptimizationTarget: Full
-OptimizationTarget: WriteEDP
//-OptimizationTarget: Area

-BufferDesignOptimization: latency

//-ForceBankA (Total AxB): 64x8
//-ForceBank (Total AxB, Active CxD): 8x16x4, 8x4
//-ForceMatA (Total AxB): 1x1
//-ForceMat (Total AxB, Active CxD): 2x2, 1x2
//-ForceMuxSenseAmp: 32
//-ForceMuxOutputLev1: 1 
//-ForceMuxOutputLev2: 1

-StackedDieCount: 1