Commit f490aa72 authored by sparshmittal's avatar sparshmittal
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Initial commit

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# Compiled Object files
*.slo
*.lo
*.o
# Compiled Dynamic libraries
*.so
*.dylib
# Compiled Static libraries
*.lai
*.la
*.a
//Copyright (c) 2015-2016, UT-Battelle, LLC. See LICENSE file in the top-level directory
// This file contains code from NVSim, (c) 2012-2013, Pennsylvania State University
//and Hewlett-Packard Company. See LICENSE_NVSim file in the top-level directory.
//No part of DESTINY Project, including this file, may be copied,
//modified, propagated, or distributed except according to the terms
//contained in the LICENSE file.
#include "Bank.h"
Bank::Bank() {
// TODO Auto-generated constructor stub
initialized = false;
invalid = false;
}
Bank::~Bank() {
// TODO Auto-generated destructor stub
}
void Bank::PrintProperty() {
cout << "Bank Properties:" << endl;
FunctionUnit::PrintProperty();
}
Bank & Bank::operator=(const Bank &rhs) {
height = rhs.height;
width = rhs.width;
area = rhs.area;
readLatency = rhs.readLatency;
writeLatency = rhs.writeLatency;
readDynamicEnergy = rhs.readDynamicEnergy;
writeDynamicEnergy = rhs.writeDynamicEnergy;
resetLatency = rhs.resetLatency;
setLatency = rhs.setLatency;
refreshLatency = rhs.refreshLatency;
resetDynamicEnergy = rhs.resetDynamicEnergy;
setDynamicEnergy = rhs.setDynamicEnergy;
refreshDynamicEnergy = rhs.refreshDynamicEnergy;
cellReadEnergy = rhs.cellReadEnergy;
cellSetEnergy = rhs.cellSetEnergy;
cellResetEnergy = rhs.cellResetEnergy;
leakage = rhs.leakage;
initialized = rhs.initialized;
invalid = rhs.invalid;
numRowMat = rhs.numRowMat;
numColumnMat = rhs.numColumnMat;
capacity = rhs.capacity;
blockSize = rhs.blockSize;
associativity = rhs.associativity;
numRowPerSet = rhs.numRowPerSet;
numActiveMatPerRow = rhs.numActiveMatPerRow;
numActiveMatPerColumn = rhs.numActiveMatPerColumn;
muxSenseAmp = rhs.muxSenseAmp;
internalSenseAmp = rhs.internalSenseAmp;
muxOutputLev1 = rhs.muxOutputLev1;
muxOutputLev2 = rhs.muxOutputLev2;
areaOptimizationLevel = rhs.areaOptimizationLevel;
memoryType = rhs.memoryType;
numRowSubarray = rhs.numRowSubarray;
numColumnSubarray = rhs.numColumnSubarray;
numActiveSubarrayPerRow = rhs.numActiveSubarrayPerRow;
numActiveSubarrayPerColumn = rhs.numActiveSubarrayPerColumn;
stackedDieCount = rhs.stackedDieCount;
partitionGranularity = rhs.partitionGranularity;
routingReadLatency = rhs.routingReadLatency;
routingWriteLatency = rhs.routingWriteLatency;
routingResetLatency = rhs.routingResetLatency;
routingSetLatency = rhs.routingSetLatency;
routingRefreshLatency = rhs.routingRefreshLatency;
routingReadDynamicEnergy = rhs.routingReadDynamicEnergy;
routingWriteDynamicEnergy = rhs.routingWriteDynamicEnergy;
routingResetDynamicEnergy = rhs.routingResetDynamicEnergy;
routingSetDynamicEnergy = rhs.routingSetDynamicEnergy;
routingRefreshDynamicEnergy = rhs.routingRefreshDynamicEnergy;
routingLeakage = rhs.routingLeakage;
mat = rhs.mat;
tsvArray = rhs.tsvArray;
return *this;
}
//Copyright (c) 2015-2016, UT-Battelle, LLC. See LICENSE file in the top-level directory
// This file contains code from NVSim, (c) 2012-2013, Pennsylvania State University
//and Hewlett-Packard Company. See LICENSE_NVSim file in the top-level directory.
//No part of DESTINY Project, including this file, may be copied,
//modified, propagated, or distributed except according to the terms
//contained in the LICENSE file.
#ifndef BANK_H_
#define BANK_H_
#include "FunctionUnit.h"
#include "Mat.h"
#include "typedef.h"
#include "TSV.h"
class Bank: public FunctionUnit {
public:
Bank();
virtual ~Bank();
/* Functions */
void PrintProperty();
virtual void Initialize(int _numRowMat, int _numColumnMat, long long _capacity,
long _blockSize, int _associativity, int _numRowPerSet, int _numActiveMatPerRow,
int _numActiveMatPerColumn, int _muxSenseAmp, bool _internalSenseAmp, int _muxOutputLev1, int _muxOutputLev2,
int _numRowSubarray, int _numColumnSubarray,
int _numActiveSubarrayPerRow, int _numActiveSubarrayPerColumn,
BufferDesignTarget _areaOptimizationLevel, MemoryType _memoryType,
int _stackedDieCount, int _paritionGranularity, int monolithicStackCount) = 0;
virtual void CalculateArea() = 0;
virtual void CalculateRC() = 0;
virtual void CalculateLatencyAndPower() = 0;
virtual Bank & operator=(const Bank &);
/* Properties */
bool initialized; /* Initialization flag */
bool invalid; /* Indicate that the current configuration is not valid, pass down to all the sub-components */
bool internalSenseAmp;
int numRowMat; /* Number of mat rows in a bank */
int numColumnMat; /* Number of mat columns in a bank */
long long capacity; /* The capacity of this bank, Unit: bit */
long blockSize; /* The basic block size in this bank, Unit: bit */
int associativity; /* Associativity, for cache design only */
int numRowPerSet; /* For cache design, the number of wordlines which a set is partitioned into */
int numActiveMatPerRow; /* For different access types */
int numActiveMatPerColumn; /* For different access types */
int muxSenseAmp; /* How many bitlines connect to one sense amplifier */
int muxOutputLev1; /* How many sense amplifiers connect to one output bit, level-1 */
int muxOutputLev2; /* How many sense amplifiers connect to one output bit, level-2 */
int numRowSubarray; /* Number of subarray rows in a mat */
int numColumnSubarray; /* Number of subarray columns in a mat */
int numActiveSubarrayPerRow; /* For different access types */
int numActiveSubarrayPerColumn; /* For different access types */
BufferDesignTarget areaOptimizationLevel;
MemoryType memoryType;
int stackedDieCount;
int partitionGranularity;
double routingReadLatency;
double routingWriteLatency;
double routingResetLatency;
double routingSetLatency;
double routingRefreshLatency;
double routingReadDynamicEnergy; /* Non-TSV routing energy. */
double routingWriteDynamicEnergy; /* Non-TSV routing energy. */
double routingResetDynamicEnergy; /* Non-TSV routing energy. */
double routingSetDynamicEnergy; /* Non-TSV routing energy. */
double routingRefreshDynamicEnergy; /* Non-TSV routing energy. */
double routingLeakage;
Mat mat;
TSV tsvArray;
};
#endif /* BANK_H_ */
//Copyright (c) 2015-2016, UT-Battelle, LLC. See LICENSE file in the top-level directory
// This file contains code from NVSim, (c) 2012-2013, Pennsylvania State University
//and Hewlett-Packard Company. See LICENSE_NVSim file in the top-level directory.
//No part of DESTINY Project, including this file, may be copied,
//modified, propagated, or distributed except according to the terms
//contained in the LICENSE file.
#include "BankWithHtree.h"
#include "formula.h"
#include "global.h"
BankWithHtree::BankWithHtree() {
// TODO Auto-generated constructor stub
initialized = false;
invalid = false;
numHorizontalAddressBitToRoute = NULL; /* The number of horizontal bits to route on level x */
numHorizontalDataDistributeBitToRoute = NULL; /* The number of horizontal data-in bits to route on level x */
numHorizontalDataBroadcastBitToRoute = NULL; /* The number of horizontal data-out bits to route on level x */
numHorizontalWire = NULL; /* The number of horizontal wires on level x */
numSumHorizontalWire = NULL; /* The number of total horizontal wires on level x */
numActiveHorizontalWire = NULL; /* The number of active horizontal wires on level x */
lengthHorizontalWire = NULL; /* The length of horizontal wires on level x, Unit: m */
numVerticalAddressBitToRoute = NULL; /* The number of vertical address bits to route on level x */
numVerticalDataDistributeBitToRoute = NULL; /* The number of vertical data-in bits to route on level x */
numVerticalDataBroadcastBitToRoute = NULL; /* The number of vertical data-out bits to route on level x */
numVerticalWire = NULL; /* The number of vertical wires on level x */
numSumVerticalWire = NULL; /* The number of total vertical wires on level x */
numActiveVerticalWire = NULL; /* The number of active vertical wires on level x */
lengthVerticalWire = NULL; /* The length of vertical wires on level 2, Unit: m */
}
BankWithHtree::~BankWithHtree() {
// TODO Auto-generated destructor stub
if (numHorizontalAddressBitToRoute)
delete [] numHorizontalAddressBitToRoute;
if (numHorizontalDataDistributeBitToRoute)
delete [] numHorizontalDataDistributeBitToRoute;
if (numHorizontalDataBroadcastBitToRoute)
delete [] numHorizontalDataBroadcastBitToRoute;
if (numHorizontalWire)
delete [] numHorizontalWire;
if (numSumHorizontalWire)
delete [] numSumHorizontalWire;
if (numActiveHorizontalWire)
delete [] numActiveHorizontalWire;
if (lengthHorizontalWire)
delete [] lengthHorizontalWire;
if (numVerticalAddressBitToRoute)
delete [] numVerticalAddressBitToRoute;
if (numVerticalDataDistributeBitToRoute)
delete [] numVerticalDataDistributeBitToRoute;
if (numVerticalDataBroadcastBitToRoute)
delete [] numVerticalDataBroadcastBitToRoute;
if (numVerticalWire)
delete [] numVerticalWire;
if (numSumVerticalWire)
delete [] numSumVerticalWire;
if (numActiveVerticalWire)
delete [] numActiveVerticalWire;
if (lengthVerticalWire)
delete [] lengthVerticalWire;
}
void BankWithHtree::Initialize(int _numRowMat, int _numColumnMat, long long _capacity,
long _blockSize, int _associativity, int _numRowPerSet, int _numActiveMatPerRow,
int _numActiveMatPerColumn, int _muxSenseAmp, bool _internalSenseAmp, int _muxOutputLev1, int _muxOutputLev2,
int _numRowSubarray, int _numColumnSubarray,
int _numActiveSubarrayPerRow, int _numActiveSubarrayPerColumn,
BufferDesignTarget _areaOptimizationLevel, MemoryType _memoryType,
int _stackedDieCount, int _partitionGranularity, int monolithicStackCount) {
if (initialized) {
/* Reset the class for re-initialization */
if (numHorizontalAddressBitToRoute)
delete [] numHorizontalAddressBitToRoute;
if (numHorizontalDataDistributeBitToRoute)
delete [] numHorizontalDataDistributeBitToRoute;
if (numHorizontalDataBroadcastBitToRoute)
delete [] numHorizontalDataBroadcastBitToRoute;
if (numHorizontalWire)
delete [] numHorizontalWire;
if (numSumHorizontalWire)
delete [] numSumHorizontalWire;
if (numActiveHorizontalWire)
delete [] numActiveHorizontalWire;
if (lengthHorizontalWire)
delete [] lengthHorizontalWire;
if (numVerticalAddressBitToRoute)
delete [] numVerticalAddressBitToRoute;
if (numVerticalDataDistributeBitToRoute)
delete [] numVerticalDataDistributeBitToRoute;
if (numVerticalDataBroadcastBitToRoute)
delete [] numVerticalDataBroadcastBitToRoute;
if (numVerticalWire)
delete [] numVerticalWire;
if (numSumVerticalWire)
delete [] numSumVerticalWire;
if (numActiveVerticalWire)
delete [] numActiveVerticalWire;
if (lengthVerticalWire)
delete [] lengthVerticalWire;
initialized = false;
invalid = false;
numHorizontalAddressBitToRoute = NULL; /* The number of horizontal bits to route on level x */
numHorizontalDataDistributeBitToRoute = NULL; /* The number of horizontal data-in bits to route on level x */
numHorizontalDataBroadcastBitToRoute = NULL; /* The number of horizontal data-out bits to route on level x */
numHorizontalWire = NULL; /* The number of horizontal wires on level x */
numSumHorizontalWire = NULL; /* The number of total horizontal wires on level x */
numActiveHorizontalWire = NULL; /* The number of active horizontal wires on level x */
lengthHorizontalWire = NULL; /* The length of horizontal wires on level x, Unit: m */
numVerticalAddressBitToRoute = NULL; /* The number of vertical address bits to route on level x */
numVerticalDataDistributeBitToRoute = NULL; /* The number of vertical data-in bits to route on level x */
numVerticalDataBroadcastBitToRoute = NULL; /* The number of vertical data-out bits to route on level x */
numVerticalWire = NULL; /* The number of vertical wires on level x */
numSumVerticalWire = NULL; /* The number of total vertical wires on level x */
numActiveVerticalWire = NULL; /* The number of active vertical wires on level x */
lengthVerticalWire = NULL; /* The length of vertical wires on level 2, Unit: m */
}
if (!_internalSenseAmp) {
invalid = true;
cout << "[Bank] Htree organization does not support external sense amplification scheme" << endl;
return;
}
if (initialized)
cout << "[Bank] Warning: Already initialized!" << endl;
numRowMat = _numRowMat;
numColumnMat = _numColumnMat;
capacity = _capacity;
blockSize = _blockSize;
associativity = _associativity;
numRowPerSet = _numRowPerSet;
internalSenseAmp = _internalSenseAmp;
areaOptimizationLevel = _areaOptimizationLevel;
memoryType = _memoryType;
stackedDieCount = _stackedDieCount;
partitionGranularity = _partitionGranularity;
int numWay = 1; /* default value for non-cache design */
/* Calculate the physical signals that are required in routing. Use double during the calculation to avoid overflow */
if (stackedDieCount > 1 /*&& partitionGranularity == 0*/) {
numAddressBit = (int)(log2((double)capacity / blockSize / associativity / stackedDieCount) + 0.1);
} else {
numAddressBit = (int)(log2((double)capacity / blockSize / associativity) + 0.1);
}
if (memoryType == data) {
numDataDistributeBit = blockSize;
numDataBroadcastBit = (int)(log2(associativity)); /* TO-DO: this is not the only way */
} else if (memoryType == tag) {
numDataDistributeBit = associativity; /* TO-DO: it seems that it only supports power of 2 here */
numDataBroadcastBit = blockSize;
} else { /* CAM */
numDataDistributeBit = 0;
numDataBroadcastBit = blockSize;
}
if (_numActiveMatPerRow > numColumnMat) {
cout << "[Bank] Warning: The number of active subarray per row is larger than the number of subarray per row!" << endl;
cout << _numActiveMatPerRow << " > " << numColumnMat << endl;
numActiveMatPerRow = numColumnMat;
} else {
numActiveMatPerRow = _numActiveMatPerRow;
}
if (_numActiveMatPerColumn > numRowMat) {
cout << "[Bank] Warning: The number of active subarray per column is larger than the number of subarray per column!" << endl;
cout << _numActiveMatPerColumn << " > " << numRowMat << endl;
numActiveMatPerColumn = numRowMat;
} else {
numActiveMatPerColumn = _numActiveMatPerColumn;
}
muxSenseAmp = _muxSenseAmp;
muxOutputLev1 = _muxOutputLev1;
muxOutputLev2 = _muxOutputLev2;
numRowSubarray = _numRowSubarray;
numColumnSubarray = _numColumnSubarray;
if (_numActiveSubarrayPerRow > numColumnSubarray) {
cout << "[Bank] Warning: The number of active subarray per row is larger than the number of subarray per row!" << endl;
cout << _numActiveSubarrayPerRow << " > " << numColumnSubarray << endl;
numActiveSubarrayPerRow = numColumnSubarray;
} else {
numActiveSubarrayPerRow = _numActiveSubarrayPerRow;
}
if (_numActiveSubarrayPerColumn > numRowSubarray) {
cout << "[Bank] Warning: The number of active subarray per column is larger than the number of subarray per column!" << endl;
cout << _numActiveSubarrayPerColumn << " > " << numRowSubarray << endl;
numActiveSubarrayPerColumn = numRowSubarray;
} else {
numActiveSubarrayPerColumn = _numActiveSubarrayPerColumn;
}
levelHorizontal = (int)(log2(numColumnMat)+0.1);
levelVertical = (int)(log2(numRowMat)+0.1);
if (levelHorizontal > 0) {
numHorizontalAddressBitToRoute = new int[levelHorizontal];
numHorizontalDataDistributeBitToRoute = new int[levelHorizontal];
numHorizontalDataBroadcastBitToRoute = new int[levelHorizontal];
numHorizontalWire = new int[levelHorizontal];
numSumHorizontalWire = new int[levelHorizontal];
numActiveHorizontalWire = new int[levelHorizontal];
lengthHorizontalWire = new double[levelHorizontal];
}
if (levelVertical > 0) {
numVerticalAddressBitToRoute = new int[levelVertical];
numVerticalDataDistributeBitToRoute = new int[levelVertical];
numVerticalDataBroadcastBitToRoute = new int[levelVertical];
numVerticalWire = new int[levelVertical];
numSumVerticalWire = new int[levelVertical];
numActiveVerticalWire = new int[levelVertical];
lengthVerticalWire = new double[levelVertical];
}
/* When H > V */
int h = levelHorizontal;
int v = levelVertical;
int rowToActive = numActiveMatPerColumn;
int columnToActive = numActiveMatPerRow;
int numAddressBitToRoute = numAddressBit;
int numDataDistributeBitToRoute = numDataDistributeBit;
int numDataBroadcastBitToRoute = numDataBroadcastBit;
/* Always route H as the first step, TO-DO: this constraint is not valid */
if (h > 0) {
if (numDataDistributeBitToRoute + numDataBroadcastBitToRoute == 0 || numAddressBitToRoute == 0) {
invalid = true;
initialized = true;
return;
}
numHorizontalAddressBitToRoute[0] = numAddressBitToRoute;
numHorizontalDataDistributeBitToRoute[0] = numDataDistributeBitToRoute;
numHorizontalDataBroadcastBitToRoute[0] = numDataBroadcastBitToRoute;
numHorizontalWire[0] = 1;
numSumHorizontalWire[0] = 1;
numActiveHorizontalWire[0] = 1;
h--;
}
int hTemp, vTemp;
hTemp = 1;
vTemp = 1;
/* If H is larger than V, then reduce H to V */
while (h > v) {
if (numDataDistributeBitToRoute + numDataBroadcastBitToRoute == 0 || numAddressBitToRoute == 0) {
invalid = true;
initialized = true;
return;
}
/* If there is possibility to reduce the data bits */
if (columnToActive > 1) {
numDataDistributeBitToRoute /= 2;
columnToActive /= 2;
numActiveHorizontalWire[levelHorizontal - h] = 2 * numActiveHorizontalWire[levelHorizontal - h - 1];
} else {
numAddressBitToRoute--;
numActiveHorizontalWire[levelHorizontal - h] = numActiveHorizontalWire[levelHorizontal - h - 1];
}
numHorizontalAddressBitToRoute[levelHorizontal - h] = numAddressBitToRoute;
numHorizontalDataDistributeBitToRoute[levelHorizontal - h] = numDataDistributeBitToRoute;
numHorizontalDataBroadcastBitToRoute[levelHorizontal - h] = numDataBroadcastBitToRoute;
numHorizontalWire[levelHorizontal - h] = 1;
numSumHorizontalWire[levelHorizontal - h] = 2 * numSumHorizontalWire[levelHorizontal - h - 1];
h--;
vTemp *= 2;
}
/* If V is larger than H, then reduce V to H */
while (v > h) {
if (numDataDistributeBitToRoute + numDataBroadcastBitToRoute == 0 || numAddressBitToRoute == 0) {
invalid = true;
initialized = true;
return;
}
/* If there is possibility to reduce the data bits on vertical */
if (rowToActive > 1) {
numDataDistributeBitToRoute /= 2;
rowToActive /= 2;
if (v == levelVertical) {
numActiveVerticalWire[0] = 2;
} else {
numActiveVerticalWire[levelVertical - v] = 2 * numActiveVerticalWire[levelVertical - v - 1];
}
} else {
numAddressBitToRoute--;
if (v == levelVertical) {
numActiveVerticalWire[0] = 1;
} else {
numActiveVerticalWire[levelVertical - v] = numActiveVerticalWire[levelVertical - v - 1];
}
}
numVerticalAddressBitToRoute[levelVertical - v] = numAddressBitToRoute;
numVerticalDataDistributeBitToRoute[levelVertical - v] = numDataDistributeBitToRoute;
numVerticalDataBroadcastBitToRoute[levelVertical - v] = numDataBroadcastBitToRoute;
numVerticalWire[levelVertical - v] = 1;
if (v == levelVertical) {
numSumVerticalWire[0] = 2;
} else {
numSumVerticalWire[levelVertical - v] = 2 * numSumVerticalWire[levelVertical - v - 1];
}
v--;
hTemp *= 2;
}
/* Reduce H an V to zero */
while (h > 0) {
if (numDataDistributeBitToRoute + numDataBroadcastBitToRoute == 0 || numAddressBitToRoute == 0) {
invalid = true;
initialized = true;
return;
}
/* If there is possibility to reduce the data bits */
if (columnToActive > 1) {
numDataDistributeBitToRoute /= 2;
columnToActive /= 2;
if (v == levelVertical) {
numActiveHorizontalWire[levelHorizontal - h] = 2 * numActiveHorizontalWire[levelHorizontal - h - 1];
} else {
numActiveHorizontalWire[levelHorizontal - h] = 2 * numActiveVerticalWire[levelVertical - v - 1];
}
} else {
numAddressBitToRoute--;
if (v == levelVertical) {
numActiveHorizontalWire[levelHorizontal - h] = numActiveHorizontalWire[levelHorizontal - h - 1];
} else {
numActiveHorizontalWire[levelHorizontal - h] = numActiveVerticalWire[levelVertical - v - 1];
}
}
numHorizontalAddressBitToRoute[levelHorizontal - h] = numAddressBitToRoute;
numHorizontalDataDistributeBitToRoute[levelHorizontal - h] = numDataDistributeBitToRoute;
numHorizontalDataBroadcastBitToRoute[levelHorizontal - h] = numDataBroadcastBitToRoute;
numHorizontalWire[levelHorizontal - h] = hTemp;
if (v == levelVertical) {
numSumHorizontalWire[levelHorizontal - h] = 2 * numSumHorizontalWire[levelHorizontal - h - 1];
} else {
numSumHorizontalWire[levelHorizontal - h] = 2 * numSumVerticalWire[levelVertical - v - 1];
}
if (numDataDistributeBitToRoute + numDataBroadcastBitToRoute == 0 || numAddressBitToRoute == 0) {
invalid = true;
initialized = true;
return;
}
/* If there is possibility to reduce the data bits on vertical */
if (rowToActive > 1) {
numDataDistributeBitToRoute /= 2;
rowToActive /= 2;
numActiveVerticalWire[levelVertical - v] = 2 * numActiveHorizontalWire[levelHorizontal - h];
} else {
numAddressBitToRoute--;
numActiveVerticalWire[levelVertical - v] = numActiveHorizontalWire[levelHorizontal - h];
}
numVerticalAddressBitToRoute[levelVertical - v] = numAddressBitToRoute;
numVerticalDataDistributeBitToRoute[levelVertical - v] = numDataDistributeBitToRoute;
numVerticalDataBroadcastBitToRoute[levelVertical - v] = numDataBroadcastBitToRoute;
if (levelHorizontal == 2) {
numVerticalWire[levelVertical - v] = vTemp;
} else {
numVerticalWire[levelVertical - v] = 2 * vTemp;
}
numSumVerticalWire[levelVertical - v] = 2 * numSumHorizontalWire[levelHorizontal - h];
h--;
v--;
hTemp *= 2;
vTemp *= 2;
}
if (numDataDistributeBitToRoute + numDataBroadcastBitToRoute == 0 || numAddressBitToRoute == 0) {
invalid = true;
initialized = true;
return;
}
if (columnToActive > 1) {
numDataDistributeBitToRoute /= 2;
columnToActive /= 2;
} else {
if (levelHorizontal > 0) {
numAddressBitToRoute--;
}
}
/* If this mat is cache data array, determine if the number of cache ways assigned to this mat is legal */
if (memoryType == data) {
if (numRowPerSet > (int)pow(2, numDataBroadcastBitToRoute)) {
/* There is no enough ways to distribute into multiple rows */
invalid = true;
initialized = true;
return;
}
}
/* If this mat is cache tag array, determine if the number of cache ways assigned to this mat is legal */
if (memoryType == tag) {
if (numRowPerSet > 1) {
/* tag array cannot have multiple rows to contain ways in a set, otherwise the bitline has to be shared */
invalid = true;
initialized = true;
return;
}
if (numDataDistributeBitToRoute == 0) {
/* This mat does not contain at least one way */
invalid = true;
initialized = true;
return;
}
}
/* Determine the number of columns in a mat */
long matBlockSize;
if (memoryType == data) { /* Data array */
/* numDataDistributeBit is the bits in a data word that is assigned to this mat */
matBlockSize = numDataDistributeBitToRoute;
numWay = (int)pow(2, numDataBroadcastBitToRoute);
/* Consider the case if each mat is a cache data array that contains multiple ways */
int numWayPerRow = numWay / numRowPerSet; /* At least 1, otherwise it is invalid, and returned already */
if (numWayPerRow > 1) { /* multiple ways per row, needs extra mux level */
/* Do mux level recalculation to contain the multiple ways */
if (cell->memCellType == DRAM || cell->memCellType == eDRAM) {
/* for DRAM, mux before sense amp has to be 1, only mux output1 and mux output2 can be used */
int numWayPerRowInLog = (int)(log2((double)numWayPerRow) + 0.1);
int extraMuxOutputLev2 = (int)pow(2, numWayPerRowInLog / 2);
int extraMuxOutputLev1 = numWayPerRow / extraMuxOutputLev2;
muxOutputLev1 *= extraMuxOutputLev1;
muxOutputLev2 *= extraMuxOutputLev2;
} else {
/* for non-DRAM, all mux levels can be used */
int numWayPerRowInLog = (int)(log2((double)numWayPerRow) + 0.1);
int extraMuxOutputLev2 = (int)pow(2, numWayPerRowInLog / 3);
int extraMuxOutputLev1 = extraMuxOutputLev2;
int extraMuxSenseAmp = numWayPerRow / extraMuxOutputLev1 / extraMuxOutputLev2;
muxSenseAmp *= extraMuxSenseAmp;
muxOutputLev1 *= extraMuxOutputLev1;
muxOutputLev2 *= extraMuxOutputLev2;
}
}
} else if (memoryType == tag) { /* Tag array */
/* numDataBroadcastBit is the tag width, numDataDistributeBit is the number of ways assigned to this mat */
matBlockSize = numDataBroadcastBitToRoute;
numWay = numDataDistributeBitToRoute;
} else { /* CAM */
matBlockSize = numDataBroadcastBitToRoute;
numWay = 1;
}
mat.Initialize(numRowSubarray, numColumnSubarray, numAddressBitToRoute, matBlockSize,