Commit f490aa72 authored by sparshmittal's avatar sparshmittal
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Initial commit

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# Compiled Object files
*.slo
*.lo
*.o
# Compiled Dynamic libraries
*.so
*.dylib
# Compiled Static libraries
*.lai
*.la
*.a
//Copyright (c) 2015-2016, UT-Battelle, LLC. See LICENSE file in the top-level directory
// This file contains code from NVSim, (c) 2012-2013, Pennsylvania State University
//and Hewlett-Packard Company. See LICENSE_NVSim file in the top-level directory.
//No part of DESTINY Project, including this file, may be copied,
//modified, propagated, or distributed except according to the terms
//contained in the LICENSE file.
#include "Bank.h"
Bank::Bank() {
// TODO Auto-generated constructor stub
initialized = false;
invalid = false;
}
Bank::~Bank() {
// TODO Auto-generated destructor stub
}
void Bank::PrintProperty() {
cout << "Bank Properties:" << endl;
FunctionUnit::PrintProperty();
}
Bank & Bank::operator=(const Bank &rhs) {
height = rhs.height;
width = rhs.width;
area = rhs.area;
readLatency = rhs.readLatency;
writeLatency = rhs.writeLatency;
readDynamicEnergy = rhs.readDynamicEnergy;
writeDynamicEnergy = rhs.writeDynamicEnergy;
resetLatency = rhs.resetLatency;
setLatency = rhs.setLatency;
refreshLatency = rhs.refreshLatency;
resetDynamicEnergy = rhs.resetDynamicEnergy;
setDynamicEnergy = rhs.setDynamicEnergy;
refreshDynamicEnergy = rhs.refreshDynamicEnergy;
cellReadEnergy = rhs.cellReadEnergy;
cellSetEnergy = rhs.cellSetEnergy;
cellResetEnergy = rhs.cellResetEnergy;
leakage = rhs.leakage;
initialized = rhs.initialized;
invalid = rhs.invalid;
numRowMat = rhs.numRowMat;
numColumnMat = rhs.numColumnMat;
capacity = rhs.capacity;
blockSize = rhs.blockSize;
associativity = rhs.associativity;
numRowPerSet = rhs.numRowPerSet;
numActiveMatPerRow = rhs.numActiveMatPerRow;
numActiveMatPerColumn = rhs.numActiveMatPerColumn;
muxSenseAmp = rhs.muxSenseAmp;
internalSenseAmp = rhs.internalSenseAmp;
muxOutputLev1 = rhs.muxOutputLev1;
muxOutputLev2 = rhs.muxOutputLev2;
areaOptimizationLevel = rhs.areaOptimizationLevel;
memoryType = rhs.memoryType;
numRowSubarray = rhs.numRowSubarray;
numColumnSubarray = rhs.numColumnSubarray;
numActiveSubarrayPerRow = rhs.numActiveSubarrayPerRow;
numActiveSubarrayPerColumn = rhs.numActiveSubarrayPerColumn;
stackedDieCount = rhs.stackedDieCount;
partitionGranularity = rhs.partitionGranularity;
routingReadLatency = rhs.routingReadLatency;
routingWriteLatency = rhs.routingWriteLatency;
routingResetLatency = rhs.routingResetLatency;
routingSetLatency = rhs.routingSetLatency;
routingRefreshLatency = rhs.routingRefreshLatency;
routingReadDynamicEnergy = rhs.routingReadDynamicEnergy;
routingWriteDynamicEnergy = rhs.routingWriteDynamicEnergy;
routingResetDynamicEnergy = rhs.routingResetDynamicEnergy;
routingSetDynamicEnergy = rhs.routingSetDynamicEnergy;
routingRefreshDynamicEnergy = rhs.routingRefreshDynamicEnergy;
routingLeakage = rhs.routingLeakage;
mat = rhs.mat;
tsvArray = rhs.tsvArray;
return *this;
}
//Copyright (c) 2015-2016, UT-Battelle, LLC. See LICENSE file in the top-level directory
// This file contains code from NVSim, (c) 2012-2013, Pennsylvania State University
//and Hewlett-Packard Company. See LICENSE_NVSim file in the top-level directory.
//No part of DESTINY Project, including this file, may be copied,
//modified, propagated, or distributed except according to the terms
//contained in the LICENSE file.
#ifndef BANK_H_
#define BANK_H_
#include "FunctionUnit.h"
#include "Mat.h"
#include "typedef.h"
#include "TSV.h"
class Bank: public FunctionUnit {
public:
Bank();
virtual ~Bank();
/* Functions */
void PrintProperty();
virtual void Initialize(int _numRowMat, int _numColumnMat, long long _capacity,
long _blockSize, int _associativity, int _numRowPerSet, int _numActiveMatPerRow,
int _numActiveMatPerColumn, int _muxSenseAmp, bool _internalSenseAmp, int _muxOutputLev1, int _muxOutputLev2,
int _numRowSubarray, int _numColumnSubarray,
int _numActiveSubarrayPerRow, int _numActiveSubarrayPerColumn,
BufferDesignTarget _areaOptimizationLevel, MemoryType _memoryType,
int _stackedDieCount, int _paritionGranularity, int monolithicStackCount) = 0;
virtual void CalculateArea() = 0;
virtual void CalculateRC() = 0;
virtual void CalculateLatencyAndPower() = 0;
virtual Bank & operator=(const Bank &);
/* Properties */
bool initialized; /* Initialization flag */
bool invalid; /* Indicate that the current configuration is not valid, pass down to all the sub-components */
bool internalSenseAmp;
int numRowMat; /* Number of mat rows in a bank */
int numColumnMat; /* Number of mat columns in a bank */
long long capacity; /* The capacity of this bank, Unit: bit */
long blockSize; /* The basic block size in this bank, Unit: bit */
int associativity; /* Associativity, for cache design only */
int numRowPerSet; /* For cache design, the number of wordlines which a set is partitioned into */
int numActiveMatPerRow; /* For different access types */
int numActiveMatPerColumn; /* For different access types */
int muxSenseAmp; /* How many bitlines connect to one sense amplifier */
int muxOutputLev1; /* How many sense amplifiers connect to one output bit, level-1 */
int muxOutputLev2; /* How many sense amplifiers connect to one output bit, level-2 */
int numRowSubarray; /* Number of subarray rows in a mat */
int numColumnSubarray; /* Number of subarray columns in a mat */
int numActiveSubarrayPerRow; /* For different access types */
int numActiveSubarrayPerColumn; /* For different access types */
BufferDesignTarget areaOptimizationLevel;
MemoryType memoryType;
int stackedDieCount;
int partitionGranularity;
double routingReadLatency;
double routingWriteLatency;
double routingResetLatency;
double routingSetLatency;
double routingRefreshLatency;
double routingReadDynamicEnergy; /* Non-TSV routing energy. */
double routingWriteDynamicEnergy; /* Non-TSV routing energy. */
double routingResetDynamicEnergy; /* Non-TSV routing energy. */
double routingSetDynamicEnergy; /* Non-TSV routing energy. */
double routingRefreshDynamicEnergy; /* Non-TSV routing energy. */
double routingLeakage;
Mat mat;
TSV tsvArray;
};
#endif /* BANK_H_ */
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//Copyright (c) 2015-2016, UT-Battelle, LLC. See LICENSE file in the top-level directory
// This file contains code from NVSim, (c) 2012-2013, Pennsylvania State University
//and Hewlett-Packard Company. See LICENSE_NVSim file in the top-level directory.
//No part of DESTINY Project, including this file, may be copied,
//modified, propagated, or distributed except according to the terms
//contained in the LICENSE file.
#ifndef BANKWITHHTREE_H_
#define BANKWITHHTREE_H_
#include "Bank.h"
class BankWithHtree: public Bank {
public:
BankWithHtree();
virtual ~BankWithHtree();
void Initialize(int _numRowMat, int _numColumnMat, long long _capacity,
long _blockSize, int _associativity, int _numRowPerSet, int _numActiveMatPerRow,
int _numActiveMatPerColumn, int _muxSenseAmp, bool _internalSenseAmp, int _muxOutputLev1, int _muxOutputLev2,
int _numRowSubarray, int _numColumnSubarray,
int _numActiveSubarrayPerRow, int _numActiveSubarrayPerColumn,
BufferDesignTarget _areaOptimizationLevel, MemoryType _memoryType,
int _stackedDieCount, int _partitionGranularity, int monolithicStackCount);
void CalculateArea();
void CalculateRC();
void CalculateLatencyAndPower();
BankWithHtree & operator=(const BankWithHtree &);
int numAddressBit; /* Number of bank address bits */
int numDataDistributeBit; /* Number of bank data bits (these bits will be distributed along with the address) */
int numDataBroadcastBit; /* Number of bank data bits (these bits will be broadcasted at every node) */
int levelHorizontal; /* The number of horizontal levels */
int levelVertical; /* The number of vertical levels */
int * numHorizontalAddressBitToRoute; /* The number of horizontal bits to route on level x */
int * numHorizontalDataDistributeBitToRoute; /* The number of horizontal data-in bits to route on level x */
int * numHorizontalDataBroadcastBitToRoute; /* The number of horizontal data-out bits to route on level x */
int * numHorizontalWire; /* The number of horizontal wire tiers on level x */
int * numSumHorizontalWire; /* The number of total horizontal wire groups on level x */
int * numActiveHorizontalWire; /* The number of active horizontal wire groups on level x */
double * lengthHorizontalWire; /* The length of horizontal wires on level x, Unit: m */
int * numVerticalAddressBitToRoute; /* The number of vertical address bits to route on level x */
int * numVerticalDataDistributeBitToRoute; /* The number of vertical data-in bits to route on level x */
int * numVerticalDataBroadcastBitToRoute; /* The number of vertical data-out bits to route on level x */
int * numVerticalWire; /* The number of vertical wire tiers on level x */
int * numSumVerticalWire; /* The number of total vertical wire groups on level x */
int * numActiveVerticalWire; /* The number of active vertical wire groups on level x */
double * lengthVerticalWire; /* The length of vertical wires on level x, Unit: m */
};
#endif /* BANKWITHHTREE_H_ */
This diff is collapsed.
//Copyright (c) 2015-2016, UT-Battelle, LLC. See LICENSE file in the top-level directory
// This file contains code from NVSim, (c) 2012-2013, Pennsylvania State University
//and Hewlett-Packard Company. See LICENSE_NVSim file in the top-level directory.
//No part of DESTINY Project, including this file, may be copied,
//modified, propagated, or distributed except according to the terms
//contained in the LICENSE file.
#ifndef BANKWITHOUTHTREE_H_
#define BANKWITHOUTHTREE_H_
#include "Bank.h"
#include "Mat.h"
#include "typedef.h"
#include "Comparator.h"
class BankWithoutHtree: public Bank {
public:
BankWithoutHtree();
virtual ~BankWithoutHtree();
/* Functions */
void Initialize(int _numRowMat, int _numColumnMat, long long _capacity,
long _blockSize, int _associativity, int _numRowPerSet, int _numActiveMatPerRow,
int _numActiveMatPerColumn, int _muxSenseAmp, bool _internalSenseAmp, int _muxOutputLev1, int _muxOutputLev2,
int _numRowSubarray, int _numColumnSubarray,
int _numActiveSubarrayPerRow, int _numActiveSubarrayPerColumn,
BufferDesignTarget _areaOptimizationLevel, MemoryType _memoryType,
int _stackedDieCount, int _partitionGranularity, int monolithicStackCount);
void CalculateArea();
void CalculateRC();
void CalculateLatencyAndPower();
BankWithoutHtree & operator=(const BankWithoutHtree &);
int numAddressBit; /* Number of bank address bits */
int numWay; /* Number of way in a mat */
int numAddressBitRouteToMat; /* Number of address bits routed to mat */
int numDataBitRouteToMat; /* Number of data bits routed to mat */
Mux globalBitlineMux;
SenseAmp globalSenseAmp;
Comparator globalComparator;
};
#endif /* BANKWITHOUTHTREE_H_ */
// This file contains code from NVSim, (c) 2012-2013, Pennsylvania State University
//and Hewlett-Packard Company. See LICENSE_NVSim file in the top-level directory.
//No part of DESTINY Project, including this file, may be copied,
//modified, propagated, or distributed except according to the terms
//contained in the LICENSE file.
#include "BasicDecoder.h"
#include "formula.h"
#include "global.h"
BasicDecoder::BasicDecoder() {
// TODO Auto-generated constructor stub
initialized = false;
}
BasicDecoder::~BasicDecoder() {
// TODO Auto-generated destructor stub
}
void BasicDecoder::Initialize(int _numAddressBit, double _capLoad, double _resLoad){
/*if (initialized)
cout << "Warning: Already initialized!" << endl;*/
/* might be re-initialized by predecodeblock */
if (_numAddressBit == 1) {
numNandInput = 0;
}
else {
numNandInput = _numAddressBit;
}
capLoad = _capLoad;
resLoad = _resLoad;
if (numNandInput == 0) {
numNandGate = 0;
double logicEffortInv = 1;
double widthInvN = MIN_NMOS_SIZE * tech->featureSize;
double widthInvP = tech->pnSizeRatio * MIN_NMOS_SIZE * tech->featureSize;
double capInv = CalculateGateCap(widthInvN, *tech) + CalculateGateCap(widthInvP, *tech);
outputDriver.Initialize(logicEffortInv, capInv, capLoad, resLoad, true, latency_first, 0); /* Always Latency First */
}
else{
double logicEffortNand;
double capNand;
if (numNandInput == 2) { /* NAND2 */
numNandGate = 4;
widthNandN = 2 * MIN_NMOS_SIZE * tech->featureSize;
logicEffortNand = (2+tech->pnSizeRatio) / (1+tech->pnSizeRatio);
} else { /* NAND3 */
numNandGate = 8;
widthNandN = 3 * MIN_NMOS_SIZE * tech->featureSize;
logicEffortNand = (3+tech->pnSizeRatio) / (1+tech->pnSizeRatio);
}
widthNandP = tech->pnSizeRatio * MIN_NMOS_SIZE * tech->featureSize;
capNand = CalculateGateCap(widthNandN, *tech) + CalculateGateCap(widthNandP, *tech);
outputDriver.Initialize(logicEffortNand, capNand, capLoad, resLoad, true, latency_first, 0); /* Always Latency First */
}
initialized = true;
}
void BasicDecoder::CalculateArea() {
if (!initialized) {
cout << "[Basic Decoder] Error: Require initialization first!" << endl;
} else {
outputDriver.CalculateArea();
if (numNandInput == 0){
height = 2 * outputDriver.height;
width = outputDriver.width;
}
else {
double hNand, wNand;
CalculateGateArea(NAND, numNandInput, widthNandN, widthNandP, tech->featureSize*40, *tech, &hNand, &wNand);
height = MAX(hNand, outputDriver.height);
width = wNand + outputDriver.width;
height *= numNandGate;
}
area = height * width;
}
}
void BasicDecoder::CalculateRC() {
if (!initialized) {
cout << "[Basic Decoder] Error: Require initialization first!" << endl;
} else {
outputDriver.CalculateRC();
if (numNandInput > 0) {
CalculateGateCapacitance(NAND, numNandInput, widthNandN, widthNandP, tech->featureSize * MAX_TRANSISTOR_HEIGHT, *tech, &capNandInput, &capNandOutput);
}
}
}
void BasicDecoder::CalculateLatency(double _rampInput) {
if (!initialized) {
cout << "[Basic Decoder] Error: Require initialization first!" << endl;
} else {
rampInput = _rampInput;
if (numNandInput == 0) {
outputDriver.CalculateLatency(rampInput);
readLatency = outputDriver.readLatency;
writeLatency = readLatency;
} else {
double resPullDown;
double capLoad;
double tr; /* time constant */
double gm; /* transconductance */
double beta; /* for horowitz calculation */
double rampInputForDriver;
resPullDown = CalculateOnResistance(widthNandN, NMOS, inputParameter->temperature, *tech) * numNandInput;
capLoad = capNandOutput + outputDriver.capInput[0];
tr = resPullDown * capLoad;
gm = CalculateTransconductance(widthNandN, NMOS, *tech);
beta = 1 / (resPullDown * gm);
readLatency = horowitz(tr, beta, rampInput, &rampInputForDriver);
outputDriver.CalculateLatency(rampInputForDriver);
readLatency += outputDriver.readLatency;
writeLatency = readLatency;
}
rampOutput = outputDriver.rampOutput;
}
}
void BasicDecoder::CalculatePower() {
if (!initialized) {
cout << "[Basic Decoder] Error: Require initialization first!" << endl;
} else {
outputDriver.CalculatePower();
double capLoad;
if (numNandInput == 0) {
leakage = 2 * outputDriver.leakage;
capLoad = outputDriver.capInput[0] + outputDriver.capOutput[0];
readDynamicEnergy = capLoad * tech->vdd * tech->vdd;
readDynamicEnergy += outputDriver.readDynamicEnergy;
readDynamicEnergy *= 1; /* only one row is activated each time */
writeDynamicEnergy = readDynamicEnergy;
} else {
/* Leakage power */
leakage = CalculateGateLeakage(NAND, numNandInput, widthNandN, widthNandP,
inputParameter->temperature, *tech) * tech->vdd;
leakage += outputDriver.leakage;
leakage *= numNandGate;
/* Dynamic energy */
capLoad = capNandOutput + outputDriver.capInput[0];
readDynamicEnergy = capLoad * tech->vdd * tech->vdd;
readDynamicEnergy += outputDriver.readDynamicEnergy;
readDynamicEnergy *= 1; /* only one row is activated each time */
writeDynamicEnergy = readDynamicEnergy;
}
}
}
void BasicDecoder::PrintProperty() {
cout << numNandInput << " to " << numNandGate << " Decoder Properties:" << endl;
FunctionUnit::PrintProperty();
}
// This file contains code from NVSim, (c) 2012-2013, Pennsylvania State University
//and Hewlett-Packard Company. See LICENSE_NVSim file in the top-level directory.
//No part of DESTINY Project, including this file, may be copied,
//modified, propagated, or distributed except according to the terms
//contained in the LICENSE file.
#ifndef BASICDECODER_H_
#define BASICDECODER_H_
#include "FunctionUnit.h"
#include "OutputDriver.h"
class BasicDecoder: public FunctionUnit {
public:
BasicDecoder();
virtual ~BasicDecoder();
/* Functions */
void PrintProperty();
void Initialize(int _numAddressBit, double _capLoad, double _resLoad);
void CalculateArea();
void CalculateRC();
void CalculateLatency(double _rampInput);
void CalculatePower();
/* Properties */
bool initialized; /* Initialization flag */
OutputDriver outputDriver;
double capLoad; /* Load capacitance, Unit: F */
double resLoad; /* Load resistance, Unit: ohm */
int numNandInput; /* Type of NAND, NAND2 or NAND3 */
int numNandGate; /* Number of NAND Gates */
double widthNandN, widthNandP;
double capNandInput, capNandOutput;
double rampInput, rampOutput;
/* TO-DO: Basic decoder so far does not take OptPriority input because the output driver is already quite fixed in this module */
};
#endif /* BASICDECODER_H_ */
Version 1.0
* Release of DESTINY
\ No newline at end of file
// This file contains code from NVSim, (c) 2012-2013, Pennsylvania State University
//and Hewlett-Packard Company. See LICENSE_NVSim file in the top-level directory.
//No part of DESTINY Project, including this file, may be copied,
//modified, propagated, or distributed except according to the terms
//contained in the LICENSE file.
#include "Comparator.h"
#include "global.h"
#include "formula.h"
#include <math.h>
Comparator::Comparator() {
initialized = false;
capLoad = 0;
rampOutput = 1e40;
// TODO Auto-generated constructor stub
}
Comparator::~Comparator() {
// TODO Auto-generated destructor stub
}
void Comparator::Initialize(int _numTagBits, double _capLoad){
if (initialized)
cout << "[Comparator] Warning: Already initialized!" << endl;
numTagBits = _numTagBits / 4; /* Assuming there are 4 quarter comparators. input tagbits is already a multiple of 4 */
capLoad = _capLoad;
widthNMOSInv[0] = 7.5 * tech->featureSize;
widthPMOSInv[0] = 12.5 * tech->featureSize;
widthNMOSInv[1] = 15 * tech->featureSize;
widthPMOSInv[1] = 25 * tech->featureSize;
widthNMOSInv[2] = 30 * tech->featureSize;
widthPMOSInv[2] = 50 * tech->featureSize;
widthNMOSInv[3] = 50 * tech->featureSize;
widthPMOSInv[3] = 100 * tech->featureSize;
widthNMOSComp = 12.5 * tech->featureSize;
widthPMOSComp = 37.5 * tech->featureSize;
initialized = true;
}
void Comparator::CalculateArea() {
if (!initialized) {
cout << "[Comparator] Error: Require initialization first!" << endl;
} else {
double totalHeight = 0;
double totalWidth = 0;
double h, w;
for (int i = 0; i < COMPARATOR_INV_CHAIN_LEN; i++) {
CalculateGateArea(INV, 1, widthNMOSInv[i], widthPMOSInv[i], tech->featureSize*40, *tech, &h, &w);
totalHeight = MAX(totalHeight, h);
totalWidth += w;
}
CalculateGateArea(NAND, 2, widthNMOSComp, 0, tech->featureSize*40, *tech, &h, &w);
totalHeight += h;
totalWidth = MAX(totalWidth, numTagBits * w);
height = totalHeight * 1; // 4 quarter comparators can have different placement, here assumes 1*4
width = totalWidth * 4;
area = height * width;
}
}
void Comparator::CalculateRC() {
if (!initialized) {
cout << "[Comparator] Error: Require initialization first!" << endl;
} else {
for (int i = 0; i < COMPARATOR_INV_CHAIN_LEN; i++) {
CalculateGateCapacitance(INV, 1, widthNMOSInv[i], widthPMOSInv[i], tech->featureSize * MAX_TRANSISTOR_HEIGHT, *tech, &(capInput[i]), &(capOutput[i]));
}
double capComp, capTemp;
CalculateGateCapacitance(NAND, 2, widthNMOSComp, 0, tech->featureSize*40, *tech, &capTemp, &capComp);
capBottom = capOutput[COMPARATOR_INV_CHAIN_LEN-1] + numTagBits * capComp;
capTop = numTagBits * capComp + CalculateDrainCap(widthPMOSComp, PMOS, tech->featureSize * MAX_TRANSISTOR_HEIGHT, *tech) + capLoad;
resBottom = CalculateOnResistance(widthNMOSInv[COMPARATOR_INV_CHAIN_LEN-1], NMOS, inputParameter->temperature, *tech);
resTop = 2 * CalculateOnResistance(widthNMOSComp, NMOS, inputParameter->temperature, *tech);
}
}
void Comparator::CalculateLatency(double _rampInput) {
if (!initialized) {
cout << "[Comparator] Error: Require initialization first!" << endl;
} else {
rampInput = _rampInput;
double resPullDown;
double capNode;
double tr; /* time constant */
double gm; /* transconductance */
double beta; /* for horowitz calculation */
double temp;
readLatency = 0;
for (int i = 0; i < COMPARATOR_INV_CHAIN_LEN - 1; i++) {
resPullDown = CalculateOnResistance(widthNMOSInv[i], NMOS, inputParameter->temperature, *tech);
capNode = capOutput[i] + capInput[i+1];
tr = resPullDown * capNode;
gm = CalculateTransconductance(widthNMOSInv[i], NMOS, *tech);
beta = 1 / (resPullDown * gm);
readLatency += horowitz(tr, beta, rampInput, &temp);
rampInput = temp; /* for next stage */
}
tr = resBottom * capBottom + (resBottom + resTop) * capTop;
readLatency += horowitz(tr, 0, rampInput, &rampOutput);
rampInput = _rampInput;
writeLatency = readLatency;
}
}
void Comparator::CalculatePower() {
if (!initialized) {
cout << "[Comparator] Error: Require initialization first!" << endl;
} else {
/* Leakage power */
leakage = 0;
for (int i = 0; i < COMPARATOR_INV_CHAIN_LEN; i++) {
leakage += CalculateGateLeakage(INV, 1, widthNMOSInv[i], widthPMOSInv[i], inputParameter->temperature, *tech)
* tech->vdd;
}
leakage += numTagBits * CalculateGateLeakage(NAND, 2, widthNMOSComp, 0, inputParameter->temperature, *tech)
* tech->vdd;
leakage *= 4;
/* Dynamic energy */
readDynamicEnergy = 0;
double capNode;
for (int i = 0; i < COMPARATOR_INV_CHAIN_LEN - 1; i++) {
capNode = capOutput[i] + capInput[i+1];
readDynamicEnergy += capNode * tech->vdd * tech->vdd;
}