Initial commit

# Compiled Object files

*.slo

*.lo

*.o

# Compiled Dynamic libraries

*.so

*.dylib

# Compiled Static libraries

*.lai

*.la

*.a

//Copyright (c) 2015-2016, UT-Battelle, LLC. See LICENSE file in the top-level directory

// This file contains code from NVSim, (c) 2012-2013,  Pennsylvania State University 

//and Hewlett-Packard Company. See LICENSE_NVSim file in the top-level directory.

//No part of DESTINY Project, including this file, may be copied,

//modified, propagated, or distributed except according to the terms

//contained in the LICENSE file.

#include "Bank.h"

Bank::Bank() {

	// TODO Auto-generated constructor stub

	initialized = false;

	invalid = false;

}

Bank::~Bank() {

	// TODO Auto-generated destructor stub

}

void Bank::PrintProperty() {

	cout << "Bank Properties:" << endl;

	FunctionUnit::PrintProperty();

}

Bank & Bank::operator=(const Bank &rhs) {

	height = rhs.height;

	width = rhs.width;

	area = rhs.area;

	readLatency = rhs.readLatency;

	writeLatency = rhs.writeLatency;

	readDynamicEnergy = rhs.readDynamicEnergy;

	writeDynamicEnergy = rhs.writeDynamicEnergy;

	resetLatency = rhs.resetLatency;

	setLatency = rhs.setLatency;

    refreshLatency = rhs.refreshLatency;

	resetDynamicEnergy = rhs.resetDynamicEnergy;

	setDynamicEnergy = rhs.setDynamicEnergy;

    refreshDynamicEnergy = rhs.refreshDynamicEnergy;

	cellReadEnergy = rhs.cellReadEnergy;

	cellSetEnergy = rhs.cellSetEnergy;

	cellResetEnergy = rhs.cellResetEnergy;

	leakage = rhs.leakage;

	initialized = rhs.initialized;

	invalid = rhs.invalid;

	numRowMat = rhs.numRowMat;

	numColumnMat = rhs.numColumnMat;

	capacity = rhs.capacity;

	blockSize = rhs.blockSize;

	associativity = rhs.associativity;

	numRowPerSet = rhs.numRowPerSet;

	numActiveMatPerRow = rhs.numActiveMatPerRow;

	numActiveMatPerColumn = rhs.numActiveMatPerColumn;

	muxSenseAmp = rhs.muxSenseAmp;

	internalSenseAmp = rhs.internalSenseAmp;

	muxOutputLev1 = rhs.muxOutputLev1;

	muxOutputLev2 = rhs.muxOutputLev2;

	areaOptimizationLevel = rhs.areaOptimizationLevel;

	memoryType = rhs.memoryType;

	numRowSubarray = rhs.numRowSubarray;

	numColumnSubarray = rhs.numColumnSubarray;

	numActiveSubarrayPerRow = rhs.numActiveSubarrayPerRow;

	numActiveSubarrayPerColumn = rhs.numActiveSubarrayPerColumn;

    stackedDieCount = rhs.stackedDieCount;

    partitionGranularity = rhs.partitionGranularity;

    routingReadLatency = rhs.routingReadLatency;

    routingWriteLatency = rhs.routingWriteLatency;

    routingResetLatency = rhs.routingResetLatency;

    routingSetLatency = rhs.routingSetLatency;

    routingRefreshLatency = rhs.routingRefreshLatency;

    routingReadDynamicEnergy = rhs.routingReadDynamicEnergy;

    routingWriteDynamicEnergy = rhs.routingWriteDynamicEnergy;

    routingResetDynamicEnergy = rhs.routingResetDynamicEnergy;

    routingSetDynamicEnergy = rhs.routingSetDynamicEnergy;

    routingRefreshDynamicEnergy = rhs.routingRefreshDynamicEnergy;

    routingLeakage = rhs.routingLeakage;

	mat = rhs.mat;

    tsvArray = rhs.tsvArray;

	return *this;

}

//Copyright (c) 2015-2016, UT-Battelle, LLC. See LICENSE file in the top-level directory

// This file contains code from NVSim, (c) 2012-2013,  Pennsylvania State University 

//and Hewlett-Packard Company. See LICENSE_NVSim file in the top-level directory.

//No part of DESTINY Project, including this file, may be copied,

//modified, propagated, or distributed except according to the terms

//contained in the LICENSE file.

#ifndef BANK_H_

#define BANK_H_

#include "FunctionUnit.h"

#include "Mat.h"

#include "typedef.h"

#include "TSV.h"

class Bank: public FunctionUnit {

public:

	Bank();

	virtual ~Bank();

	/* Functions */

	void PrintProperty();

	virtual void Initialize(int _numRowMat, int _numColumnMat, long long _capacity,

			long _blockSize, int _associativity, int _numRowPerSet, int _numActiveMatPerRow,

			int _numActiveMatPerColumn, int _muxSenseAmp, bool _internalSenseAmp, int _muxOutputLev1, int _muxOutputLev2,

			int _numRowSubarray, int _numColumnSubarray,

			int _numActiveSubarrayPerRow, int _numActiveSubarrayPerColumn,

			BufferDesignTarget _areaOptimizationLevel, MemoryType _memoryType,

            int _stackedDieCount, int _paritionGranularity, int monolithicStackCount) = 0;

	virtual void CalculateArea() = 0;

	virtual void CalculateRC() = 0;

	virtual void CalculateLatencyAndPower() = 0;

	virtual Bank & operator=(const Bank &);

	/* Properties */

	bool initialized;	/* Initialization flag */

	bool invalid;		/* Indicate that the current configuration is not valid, pass down to all the sub-components */

	bool internalSenseAmp;

	int numRowMat;		/* Number of mat rows in a bank */

	int numColumnMat;	/* Number of mat columns in a bank */

	long long capacity;		/* The capacity of this bank, Unit: bit */

	long blockSize;		/* The basic block size in this bank, Unit: bit */

	int associativity;	/* Associativity, for cache design only */

	int numRowPerSet;		/* For cache design, the number of wordlines which a set is partitioned into */

	int numActiveMatPerRow;	/* For different access types */

	int numActiveMatPerColumn;	/* For different access types */

	int muxSenseAmp;	/* How many bitlines connect to one sense amplifier */

	int muxOutputLev1;	/* How many sense amplifiers connect to one output bit, level-1 */

	int muxOutputLev2;	/* How many sense amplifiers connect to one output bit, level-2 */

	int numRowSubarray;		/* Number of subarray rows in a mat */

	int numColumnSubarray;	/* Number of subarray columns in a mat */

	int numActiveSubarrayPerRow;	/* For different access types */

	int numActiveSubarrayPerColumn;	/* For different access types */

	BufferDesignTarget areaOptimizationLevel;

	MemoryType memoryType;

    int stackedDieCount;

    int partitionGranularity;

    double routingReadLatency;

    double routingWriteLatency;

    double routingResetLatency;

    double routingSetLatency;

    double routingRefreshLatency;

    double routingReadDynamicEnergy; /* Non-TSV routing energy. */

    double routingWriteDynamicEnergy; /* Non-TSV routing energy. */

    double routingResetDynamicEnergy; /* Non-TSV routing energy. */

    double routingSetDynamicEnergy; /* Non-TSV routing energy. */

    double routingRefreshDynamicEnergy; /* Non-TSV routing energy. */

    double routingLeakage;

	Mat mat;

    TSV tsvArray;

};

#endif /* BANK_H_ */

//Copyright (c) 2015-2016, UT-Battelle, LLC. See LICENSE file in the top-level directory

// This file contains code from NVSim, (c) 2012-2013,  Pennsylvania State University 

//and Hewlett-Packard Company. See LICENSE_NVSim file in the top-level directory.

//No part of DESTINY Project, including this file, may be copied,

//modified, propagated, or distributed except according to the terms

//contained in the LICENSE file.

#ifndef BANKWITHHTREE_H_

#define BANKWITHHTREE_H_

#include "Bank.h"

class BankWithHtree: public Bank {

public:

	BankWithHtree();

	virtual ~BankWithHtree();

	void Initialize(int _numRowMat, int _numColumnMat, long long _capacity,

			long _blockSize, int _associativity, int _numRowPerSet, int _numActiveMatPerRow,

			int _numActiveMatPerColumn, int _muxSenseAmp, bool _internalSenseAmp, int _muxOutputLev1, int _muxOutputLev2,

			int _numRowSubarray, int _numColumnSubarray,

			int _numActiveSubarrayPerRow, int _numActiveSubarrayPerColumn,

			BufferDesignTarget _areaOptimizationLevel, MemoryType _memoryType,

            int _stackedDieCount, int _partitionGranularity, int monolithicStackCount);

	void CalculateArea();

	void CalculateRC();

	void CalculateLatencyAndPower();

	BankWithHtree & operator=(const BankWithHtree &);

	int numAddressBit;		/* Number of bank address bits */

	int numDataDistributeBit;	/* Number of bank data bits (these bits will be distributed along with the address) */

	int numDataBroadcastBit;	/* Number of bank data bits (these bits will be broadcasted at every node) */

	int levelHorizontal;			/* The number of horizontal levels */

	int levelVertical;				/* The number of vertical levels */

	int * numHorizontalAddressBitToRoute;  /* The number of horizontal bits to route on level x */

	int * numHorizontalDataDistributeBitToRoute;	/* The number of horizontal data-in bits to route on level x */

	int * numHorizontalDataBroadcastBitToRoute;		/* The number of horizontal data-out bits to route on level x */

	int * numHorizontalWire;        /* The number of horizontal wire tiers on level x */

	int * numSumHorizontalWire;     /* The number of total horizontal wire groups on level x */

	int * numActiveHorizontalWire;  /* The number of active horizontal wire groups on level x */

	double * lengthHorizontalWire;	/* The length of horizontal wires on level x, Unit: m */

	int * numVerticalAddressBitToRoute;	/* The number of vertical address bits to route on level x */

	int * numVerticalDataDistributeBitToRoute;	/* The number of vertical data-in bits to route on level x */

	int * numVerticalDataBroadcastBitToRoute;	/* The number of vertical data-out bits to route on level x */

	int * numVerticalWire;          /* The number of vertical wire tiers on level x */

	int * numSumVerticalWire;       /* The number of total vertical wire groups on level x */

    int * numActiveVerticalWire;    /* The number of active vertical wire groups on level x */

	double * lengthVerticalWire;	/* The length of vertical wires on level x, Unit: m */

};

#endif /* BANKWITHHTREE_H_ */